DUAL GATE ELECTRONIC MEMORY CELL AND DEVICE WITH DUAL GATE ELECTRONIC MEMORY CELLS

• US 20120139025A1
• Filed: 12/01/2011
• Published: 06/07/2012
• Est. Priority Date: 12/02/2010
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Molas, Gabriel, Gely, Marc
• Granted Patent: US 8,710,574 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A memory cell including:

• • an active area having a channel provided between a source and a drain,
  • a first gate provided on a first part of the channel,
  • a portion of a first lateral spacer provided against a lateral flank of the first gate, a part of which forms a second gate provided on a second part of the channel,
  • one of two gates forming a storing gate,
  • the memory cell further including a portion of a second lateral spacer provided against a lateral flank of a block provided on the semi-conductor layer, the second lateral spacer being in contact with the first lateral spacer, the first and second lateral spacers being composed of similar materials, said portion of the second lateral spacer forming a part of an electrical contact pad electrically connected to the second gate.

Claims

1. An electronic memory cell including at least:

one active area formed in a semi-conductor layer and including a channel provided between a source and a drain,

one first gate provided at least on one first part of the channel,

at least one portion of a first lateral spacer provided against at least one lateral flank of the first gate, a part of which forms a second gate provided on at least one second part of the channel,

one of the first or the second gate further including a stack of layers, of which at least one of said layers is capable of storing electrical charges,

the memory cell further including at least one portion of a second lateral spacer provided against at least one lateral flank of a block distinct from the first gate and provided on the semi-conductor layer, the second lateral spacer being in contact with the first lateral spacer, the first and second lateral spacers being composed of similar materials, said portion of the second lateral spacer forming at least one part of an electrical contact pad electrically connected to the second gate.

2. The electronic memory cell according to claim 1, wherein the portion of the first lateral spacer is rectilinear.

3. The electronic memory cell according to claim 1, wherein the portion of the first lateral spacer is provided against two lateral flanks of the first gate which are distinct and perpendicular to each other.

4. The electronic memory cell according to claim 1, wherein the block is formed by materials similar to those forming a part of the first gate.

5. The electronic memory cell according to claim 1, wherein the layer capable of storing electrical charges of said stack of layers is provided between two dielectric material layers of said stack.

6. The electronic memory cell according to claim 1, wherein, when the second gate includes said stack of layers, the second lateral spacer is formed by a part of the layers of said stack.

7. The electronic memory cell according to claim 1, wherein the electrical contact pad is partly formed by the portion of the first spacer.

8. The electronic memory cell according to claim 1, further including at least one portion of a third lateral spacer provided against at least one lateral flank of a second block and in contact with the second lateral spacer, and wherein the first, second and third lateral spacers are composed of similar materials, the electrical contact pad being partly formed by the portion of the third lateral spacer.

9. The electronic memory cell according to claim 8, wherein the first and second blocks are aligned with respect to each other along a direction perpendicular to a source-drain direction.

10. The electronic memory cell according to claim 8, further including at least one portion of several other lateral spacers provided against at least one lateral flank of several other blocks and in contact with the second lateral spacer and/or the third lateral spacer and/or one of said other lateral spacers, and wherein the different lateral spacers are composed of similar materials, the electrical contact pad being also formed by at least one part of the portions of said other lateral spacers.

11. The electronic memory cell according to claim 1, wherein the first lateral spacer is provided against all the lateral flanks of the first gate and/or the second lateral spacer is provided against all the lateral flanks of the block and/or, when the electrical contact pad is partly formed by the portion of the third lateral spacer, the third lateral spacer is provided against all the lateral flanks of the second block and/or, when the electrical contact pad is formed by at least one part of the portions of said other lateral spacers, said other lateral spacers are provided against all the lateral flanks of said other blocks.

19. A memory device including a plurality of memory cells according to claim 1, provided in an array and electrically connected with each other according to a NOR type architecture.

20. The memory device according to claim 19, wherein the second lateral spacers of two adjacent memory cells are provided against two opposite lateral flanks of a block common to both adjacent memory cells.

21. The memory device according to claim 19, wherein, when the electrical contact pads of two adjacent memory cells are formed by second and third lateral spacers, said third lateral spacers are provided against two opposite lateral flanks of a second block common to both adjacent memory cells.

12. A method for making an electronic memory cell including at least the steps of:

making, in a semi-conductor layer an active area including a channel provided between a source and a drain,

making a first gate provided at least on one first part of the channel, and at least one block distinct from the first gate and provided on the semi-conductor layer,

depositing a plurality of material layers for forming at least one second gate on at least one second part of the channel, said material layers covering at least the semi-conductor layer, the active area, the first gate and the block,

anisotropically etching said material layers such that a first remaining portion of said material layers forms a first lateral spacer provided against lateral flanks of the first gate, a part of the first lateral spacer forming the second gate, and such that a second remaining portion of said material layers forms a second lateral spacer provided against lateral flanks of the block and in contact with the first lateral spacer, a portion of the second lateral spacer forming at least one part of an electrical contact pad electrically connected to the second gate,

one the first or the second gate including a stack of layers, of which at least one of said layers is capable of storing electrical charges.

13. The method according to claim 12, wherein the plurality of material layers for forming the second gate comprises at least one electrically conducting layer provided on at least one dielectric layer.

14. The method according to claim 12, wherein the block and the first gate are made from the same material layers.

15. The method according to claim 12, wherein, upon making the first gate, a second block is also made on the semi-conductor layer, and wherein the step of anisotropically etching also forms a third lateral spacer provided against lateral flanks of the second block, at least one portion of the third lateral spacer being in contact with the second lateral spacer and forming at least one part of the electrical contact pad.

16. The method according to claim 15, wherein, upon making the first gate, several other blocks are also made on the semi-conductor layer, and wherein the step of anisotropically etching also forms several other lateral spacers provided against lateral flanks of said other blocks, at least one portion of said other lateral spacers being in contact with the second lateral spacer and/or the third lateral spacer and/or one of said other lateral spacers, the electrical contact pad being also formed by at least one part of the portions of said other lateral spacers.

17. The method according to claim 12, further including, after the anisotropically etching of said material layers, implementing a photolithography and etching of the first and/or second and/or third lateral spacer and/or of said other lateral spacers, such that remaining portions of the first and/or second and/or third lateral spacer and/or of said other lateral spacers form the second gate and the electrical contact pad.

18. The method according to claim 12, wherein, when the second gate includes said stack of layers, the second lateral spacer is formed by a part of the layers of said stack.

22. A method for making a memory device including at least the steps of:

making a plurality of memory cells provided in an array, including, for making at least one memory cell of each column of the array, implementing a making method according to claim 12,

making electrical interconnections of the plurality of memory cells such that the memory cells are electrically connected between each other according to a NOR type architecture.