SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20120139047A1
• Filed: 02/27/2011
• Published: 06/07/2012
• Est. Priority Date: 11/29/2010
• Status: Abandoned Application

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: Zhao, Chao, Luo, Jun
• Application Number:
  US13/380,096
• Publication Number:
  US 20120139047A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

Disclosed is a semiconductor device, comprising a substrate, a channel region in the substrate, source/drain regions on both sides of the channel region, a gate structure on the channel region, and gate sidewall spacers formed on the sidewalls of the gate structure, characterized in that each of the source/drain regions comprises an epitaxially grown metal silicide region, and dopant segregation regions are formed at the interfaces between the epitaxially grown metal silicide source/drain regions and the channel region. By employing the semiconductor device and the method for manufacturing the same according to embodiments of the present invention, the Schottkey Barrier Height of the MOSFETs with epitaxially grown ultrathin metal silicide source/drain may be lowered, thereby improving the driving capability.

Claims

1. A semiconductor device, comprising a substrate, a channel region in the substrate, source/drain regions on both sides of the channel region, a gate structure on the channel region, and gate sidewall spacers formed on both sidewalls of the gate structure, characterized in that:

each of the source/drain regions comprises epitaxially grown metal silicide, and a dopant segregation region is formed at the interface between each of the source/drain regions and the channel region.

2. The semiconductor device according to claim 1, characterized in that the material of the epitaxially grown ultrathin metal silicide source/drain regions is one of NiSi_2-y, Ni_1-xPt_xSi_2-y, CoSi_2-y and Ni_1-xCo_xSi_2-y, wherein x is greater than 0 but less than 1, and y is greater than or equal to 0 but less than 1.

3. The semiconductor device according to claim 1, characterized in that the thickness of the epitaxially grown metal silicide source/drain regions is less than or equal to 15 nm.

4. The semiconductor device according to claim 1, characterized in that for p-type MOSFETs with epitaxially grown ultrathin metal silicide source/drain, the dopants are one or more of boron B, aluminum Al, gallium Ga, indium In, and etc.;

for n-type MOSFETs with epitaxially grown ultrathin metal silicide source/drain, the dopants are one or more of nitrogen N, phosphorus P, arsenic As, oxygen O, sulphur S, selenium Se, tellurium Te, fluorine F, and chlorine Cl.

5. The semiconductor device according to claim 1, characterized in that the substrate is a bulk-silicon substrate or a semiconductor-on-insulator substrate.

6. A method for manufacturing a semiconductor device, comprising:

forming a gate structure and gate sidewall spacers on the substrate;

depositing a metal layer that covers the substrate, the gate structure, and the gate sidewall spacers;

performing a first annealing such that the metal layer on both sides of the gate reacts with the substrate to form epitaxially grown metal silicide layers;

stripping un-reacted metal layer, such that the epitaxially grown metal silicide layers form source/drain regions of the device, and a portion of the semiconductor substrate beneath the gate structure forms the channel region;

implanting dopants into the epitaxially grown ultrathin silicide source/drain regions; and

performing a second annealing to form dopant segregation regions at the interfaces between the epitaxially grown ultrathin silicide source/drain regions and the channel region.

7. The method according to claim 6, wherein the material of the epitaxially grown ultrathin metal silicide is one of NiSi_2-y, Ni_1-xPt_xSi_2-y, CoSi_2-y and Ni_1-xCo_xSi_2-y, wherein x is greater than 0 but less than 1, and y is greater than or equal to 0 but less than 1.

8. The method according to claim 6, wherein for p-type MOSFETs with epitaxially grown ultrathin metal silicide source/drain, the dopants are one or more of boron B, aluminum Al, gallium Ga, indium In, and etc.;

for n-type MOSFETs with epitaxially grown ultrathin metal silicide source/drain, the dopants are one or more of nitrogen N, phosphorus P, arsenic As, oxygen O, sulphur S, selenium Se, tellurium Te, fluorine F, and chlorine Cl.

9. The method according to claim 6, wherein the temperature for the first annealing and/or for the second annealing is in a range of 500-850°

C.

10. The method according to claim 6, wherein the implantation dosage is in a range from 1×

10¹⁴ to 1×

10¹⁶ cm<sup>−

2</sup>.

11. The method according to claim 6, wherein the thickness of the metal layer is less than or equal to 5 nm.

12. The method according to claim 6, wherein the substrate is a bulk-silicon substrate or a semiconductor-on-insulator substrate.