Device Having Adjustable Channel Stress and Method Thereof

• US 20120139054A1
• Filed: 05/16/2011
• Published: 06/07/2012
• Est. Priority Date: 12/06/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Xu, Qiuxia, Chen, Dapeng, Yin, Huaxiang
• Granted Patent: US 8,384,162 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Claims

1. An MOS device (200, 300), comprising:

a semiconductor substrate (202, 302);

a channel formed on the semiconductor substrate (202, 302);

a gate dielectric layer (204, 304) formed on the channel;

a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and

a source and a drain formed on both sides of the gate;

wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel.

2. The MOS device of claim 1, further comprising at least one of stress sidewalls (207, 307) formed on both sides of the gate for generating a second stress to be applied to the channel, a stress source (208, 308) embedded into the source and drain areas for generating a third stress to be applied to the channel, and a stress liner (210, 310) formed on the MOS device (200, 300) for generating a fourth stress to be applied to the channel such that the mobility of carriers in the channel of the MOS device is enhanced.

3. The MOS device of claim 2, wherein the MOS device is an NMOS device, the gate conductor is in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress, and the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress.

4. The MOS device of claim 3, wherein α

satisfies 45°

<

α

<

90°

.

5. The MOS device of claim 2, wherein the MOS device is an NMOS device, wherein the gate conductor is in an inverted trapezoid shape with an angle α

between its side and bottom, being larger than 90°

, such that the first stress is compressive stress, and at least one of the second stress, the third stress, and the fourth stress is tensile stress, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress.

6. The MOS device of claim 2, wherein the MOS device is a PMOS device, the gate conductor is in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

7. The MOS device of claim 6, wherein α

satisfies 90°

<

α

<

135°

.

8. The MOS device of claim 2, wherein the MOS device is a PMOS device, the gate conductor is in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress, and at least one of the second stress, the third stress, and the fourth stress is compressive stress, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

18. A CMOS device, comprising a first type of transistor and a second type of transistor which is complementary thereto, wherein the first type of transistor and the second type of transistor respectively comprise the MOS device of claim 1.

19. The CMOS device of claim 18, wherein the MOS device further comprises at least one of stress sidewalls (407A, 407B) formed on both sides of the gate for generating a second stress to be applied to the channel, a stress source (408A, 408B) embedded into the source and drain areas for generating a third stress to be applied to the channel, and a stress liner (410A, 410B) formed on the MOS device (400A, 400B) for generating a fourth stress to be applied to the channel such that the mobility of carriers in the channel of the MOS device is enhanced.

20. The CMOS device of claim 19, the first type of transistor is an NMOS device, the gate conductor is in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress, and the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress; and

the second type of transistor is a PMOS device, the gate conductor is in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

21. The CMOS device of claim 20, wherein the angle α

between the side and bottom of the gate conductor of the NMOS device satisfies 45°

<

α

<

90°

, and the angle α

between the side and bottom of the gate conductor of the PMOS device satisfies 90°

<

α

<

135°

.

22. The CMOS device of claim 19, wherein the first type of transistor is an NMOS device, the gate conductor is in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and at least one of the second stress, the third stress, and the fourth stress is tensile stress, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress; and

the second type of transistor is a PMOS device, the gate conductor is in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress, and at least one of the second stress, the third stress, and the fourth stress is compressive stress, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

9. A method for manufacturing an MOS device, comprising:

providing a semiconductor substrate (202, 302);

forming a channel on the semiconductor substrate (202, 302);

forming a gate dielectric layer (204, 304) on the channel;

forming a gate conductor (206, 306) on the gate dielectric layer (204, 304); and

forming a source and a drain on both sides of the gate;

wherein the shape of the gate conductor (206, 306) is changed by an etching process to change the first stress applied to the channel, so as to adjust the mobility of carriers in the channel.

10. The method for manufacturing the MOS device of claim 9, wherein the etching process is Reactive Ion Etching (RIE).

11. The method for manufacturing the MOS device of claim 10, further comprising at least one of the following steps:

forming stress sidewalls (207, 307) on both sides of the gate so as to generate a second stress to be applied to the channel;

embedding a stress source (208, 308) into the source and drain areas so as to generate a third stress to be applied to the channel; and

forming a stress liner (210, 310) on the MOS device (200, 300) so as to generate a fourth stress to be applied to the channel such that the mobility of carriers in the channel of the MOS device is enhanced.

12. The method for manufacturing the MOS device of claim 11, wherein the MOS device is an NMOS device, the RIE, by using the reaction gas having anisotropic etching ability and controlling the throughput of the reactive polymer of the anisotropic etching, forms the gate conductor in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress; and

wherein the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, and the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress.

13. The method for manufacturing the MOS device of claim 12, wherein the angle α

between the side and bottom of the gate conductor satisfies 45°

<

α

<

90°

.

14. The method for manufacturing the MOS device of claim 11, wherein the MOS device is an NMOS device, the RIE, by using the reaction gas having isotropic etching ability and controlling the lateral quantity of the isotropic etching, forms the gate conductor in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and wherein at least one of the second stress, the third stress, and the fourth stress is tensile stress, and the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress.

15. The method for manufacturing the MOS device of claim 11, wherein the MOS device is a PMOS device, the RIE, by using the reaction gas having isotropic etching ability and controlling the lateral quantity of the isotropic etching, forms the gate conductor in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and wherein the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, and the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

16. The method for manufacturing the MOS device of claim 15, wherein the angle α

between the side and bottom of the gate conductor satisfies 90°

<

α

<

135°

.

17. The method for manufacturing the MOS device of claim 11, wherein the MOS device is a PMOS device, the RIE, by using the reaction gas having anisotropic etching ability and controlling the throughput of the reactive polymer of the anisotropic etching, forms the gate conductor in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress; and

wherein at least one of the second stress, the third stress, and the fourth stress is compressive stress, and the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

23. A method for manufacturing a CMOS device, comprising:

forming a first type of transistor and a second type of transistor which is complementary thereto, wherein forming the first type of transistor and the second type of transistor respectively comprises performing the steps of claim 9.

24. The method for manufacturing the CMOS device of claim 23, wherein the etching process is Reactive Ion Etching (RIE).

25. The method for manufacturing the CMOS device of claim 24, further comprising at least one of the following steps:

forming stress sidewalls (407A, 407B) on both sides of the gate so as to generate a second stress to be applied to the channel;

embedding a stress source (408A, 408B) into the source and drain areas so as to generate a third stress to be applied to the channel; and

forming a stress liner (410A, 410B) on the MOS device (400A, 400B) so as to generate a fourth stress to be applied to the channel such that the mobility of carriers in the channel of the MOS device is enhanced.

26. The method for manufacturing the CMOS device of claim 25, wherein the first type of transistor is formed as an NMOS device, the RIE, by using the reaction gas having anisotropic etching ability and controlling the throughput of the reactive polymer of the anisotropic etching, forms the gate conductor of the NMOS device in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress; and

wherein the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, and the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress; and

the second type of transistor is formed as a PMOS device, the RIE, by using the reaction gas having isotropic etching ability and controlling the lateral quantity of isotropic etching, forms the gate conductor of the PMOS device in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and wherein the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, and the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.

27. The method for manufacturing the CMOS device of claim 26, wherein the angle α

between the side and bottom of the gate conductor of the NMOS device satisfies 45°

<

α

<

90°

, and the angle α

between the side and bottom of the gate conductor of the PMOS device satisfies 90°

<

α

<

135°

.

28. The method for manufacturing the CMOS device of claim 25, wherein the first type of transistor is formed as an NMOS device, the RIE, by using the reaction gas having isotropic etching ability and controlling the lateral quantity of isotropic etching, forms the gate conductor of the NMOS device in an inverted trapezoid shape with an angle α

between its side and bottom being larger than 90°

, such that the first stress is compressive stress, and at least one of the second stress, the third stress, and the fourth stress is tensile stress, and the sum of the first stress, the second stress, the third stress, and the fourth stress is tensile stress; and

the second type of transistor is formed as a PMOS device, the RIE, by using the reaction gas having anisotropic etching ability and controlling the throughput of the reactive polymer of the anisotropic etching, forms the gate conductor of the PMOS device in a regular trapezoid shape with an angle α

between its side and bottom being less than 90°

, such that the first stress is tensile stress, and at least one of the second stress, the third stress, and the fourth stress is compressive stress, and the sum of the first stress, the second stress, the third stress, and the fourth stress is compressive stress.