Self-Aligned Contact For Replacement Gate Devices

• US 20120139061A1
• Filed: 12/02/2010
• Published: 06/07/2012
• Est. Priority Date: 12/02/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ramachandran, Ravikumar, Li, Ying, Wise, Richard S.
• Granted Patent: US 8,426,300 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

Claims

1. A method of forming a semiconductor structure comprising:

forming a gate electrode and a planarization dielectric layer on a semiconductor substrate, wherein a top metallic surface of said gate electrode is coplanar with a top surface of said planarization dielectric layer;

recessing a top surface of said gate electrode relative to said top surface of said planarization dielectric layer;

forming an etch stop layer contiguously on said recessed top surface of said gate electrode and on said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate electrode and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion;

forming a contact-level dielectric layer over said etch stop layer; and

forming a via hole extending at least through said contact-level dielectric layer, said first portion of said etch stop layer, and a portion of said planarization dielectric layer, wherein said via hole is vertically spaced from said gate electrode by said second portion of said etch stop layer.

2. The method of claim 1, wherein said etch stop layer is formed by a conformal deposition so that said first portion and a center region of said second portion of said etch stop layer have a same composition and a same thickness.

3. The method of claim 2, wherein said etch stop layer is formed so that a peripheral region of said second portion has sidewalls that are vertically coincident with sidewalls of said gate electrode, and extends from a level coplanar with a bottom surface of said center region of said second portion to a level coplanar with a top surface of said first portion.

4. The method of claim 1, wherein said etch stop layer is formed by depositing a dielectric material, wherein said dielectric material has a different composition than said contact-level dielectric layer and said planarization dielectric layer.

5. The method of claim 4, wherein said etch stop layer is formed by depositing a dielectric material having a chemical composition of SiC_xO_yH_z, SiN_wC_xO_yH_z, SiC_xH_z, or SiN_wC_xH_z, wherein each of w, x, y, and z independently has a value greater than 0 and less than 0.75.

6. The method of claim 5, wherein each of said contact-level dielectric layer and said planarization dielectric layer is formed by depositing a material selected from undoped silicate glass (USG), doped silicate glass, silicon nitride, organsilicate glass (OSG), undoped silicon oxynitride, and doped silicon oxynitride.

7. The method of claim 1, wherein said via hole includes a first via hole portion that does not overlie said gate electrode and a second via hole portion that overlies said gate electrode, and said first and second via hole portions are contiguously connected to each other.

8. The method of claim 1, further comprising forming a contact via structure by filling said via hole with a conductive material, wherein said gate electrode is spaced from said contact via structure by said etch stop layer and a dielectric gate spacer.

9. The method claim 1, wherein said gate electrode is a replacement gate electrode formed by:

forming a disposable gate structure on said semiconductor substrate; and

replacing said disposable gate structure with a gate dielectric and at least one conductive material, wherein said gate electrode is a remaining portion of said at least one conductive material after removing said at least one conductive material from above a top surface of said planarization dielectric layer.

10. The method of claim 9, further comprising:

forming a dielectric gate spacer on sidewalls of said disposable gate structure; and

forming a contact via structure through said contact-level dielectric layer, said etch stop layer, and said planarization dielectric layer, wherein said contact via structure is spaced from said gate electrode by said etch stop layer and said dielectric gate spacer.

11. The method of claim 9, wherein said at least one conductive material includes at least a titanium nitride portion and an aluminum portion, and said method includes:

employing a wet etch solution including ammonium hydroxide and hydrogen peroxide to etch said titanium nitride portion; and

employing a solution including at least sulfuric acid and hydrogen peroxide or a dilute hydrofluoric acid-containing solution to etch said aluminum portion.

12. The method of claim 9, wherein said at least one conductive material includes at least a tantalum nitride portion or a titanium nitride portion, and said method includes employing a chemical downstream etch (CDE) to etch said tantalum nitride portion or said titanium nitride portion, wherein said CDE employs at least one of CHF₃, CF₄, and Cl₂ and does not generate plasma directly on said gate stack.

13. The method of claim 9, further comprising:

forming another gate electrode concurrently with formation of said gate electrode on said semiconductor substrate, wherein a top metallic surface of said other gate electrode is coplanar with said top surface of said planarization dielectric layer; and

covering said other gate electrode with a patterned mask layer, wherein said patterned mask layer does not overlie said gate electrode, and wherein said other gate electrode is not recessed while said top surface of said gate electrode is recessed relative to said top surface of said planarization dielectric layer.

14. A semiconductor structure comprising:

a gate electrode located on a semiconductor substrate;

a planarization dielectric layer laterally surrounding said gate electrode, wherein a top surface of said gate electrode is recessed relative to a top surface of said planarization dielectric layer;

an etch stop layer contiguously located on said recessed top surface of said gate electrode and said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate electrode and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion;

a contact-level dielectric layer overlying said planarization dielectric layer; and

a contact via structure extending through said contact-level dielectric layer, said etch stop layer, and said planarization dielectric layer, wherein a portion of said contact via structure overlies said gate electrode and is vertically spaced by said second portion of said etch stop layer.

15. The semiconductor structure of claim 14, wherein said first portion and a center region of said second portion of said etch stop layer have a same composition and a same thickness.

16. The semiconductor structure of claim 15, wherein a peripheral region of said second portion has sidewalls that are vertically coincident with sidewalls of said gate electrode, and extends from a level coplanar with a bottom surface of said center region of said second portion to a level coplanar with a top surface of said first portion.

17. The semiconductor structure of claim 14, wherein said etch stop layer comprises a dielectric material having a different composition than said contact-level dielectric layer and said planarization dielectric layer.

18. The semiconductor structure of claim 17, wherein said etch stop layer comprises a material having a chemical composition of SiC_xO_yH_z, SiN_wC_xO_yH_z, SiC_xH_z, or SiN_wC_xH_z, wherein each of w, x, y, and z independently has a value greater than 0 and less than 0.75.

19. The semiconductor structure of claim 18, wherein each of said contact-level dielectric layer and said planarization dielectric layer includes a material selected from undoped silicate glass (USG), doped silicate glass, silicon nitride, organsilicate glass (OSG), undoped silicon oxynitride, and doped silicon oxynitride.

20. The semiconductor structure of claim 14, further comprising a dielectric gate spacer laterally surrounding said gate electrode and is laterally surrounded by said planarization dielectric layer, wherein said contact via structure is spaced from said gate electrode by said etch stop layer and said dielectric gate spacer.