SELF-ALIGNED CONTACT COMBINED WITH A REPLACEMENT METAL GATE/HIGH-K GATE DIELECTRIC
First Claim
1. A method of forming a semiconductor device comprising:
- forming a replacement gate structure on a portion of a substrate, wherein source regions and drain regions are formed in opposing sides of the portion of the substrate that the replacement gate structure is formed on;
forming an intralevel dielectric on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure;
removing the replacement gate structure to provide an opening to an exposed portion of the substrate;
forming a high-k dielectric spacer on sidewalls of the opening;
forming a gate dielectric on the exposed portion of the substrate;
forming a functioning gate structure within the opening on the gate dielectric, wherein an upper surface of the functioning gate structure is a high-k dielectric capping layer;
andforming contact vias through the interlevel dielectric layer to at least one of the source region and the drain region, wherein an etch that provides the opening for the contact via is selective to the high-k dielectric spacer and the high-k dielectric capping layer.
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Accused Products
Abstract
A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.
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Citations
20 Claims
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1. A method of forming a semiconductor device comprising:
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forming a replacement gate structure on a portion of a substrate, wherein source regions and drain regions are formed in opposing sides of the portion of the substrate that the replacement gate structure is formed on; forming an intralevel dielectric on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure; removing the replacement gate structure to provide an opening to an exposed portion of the substrate; forming a high-k dielectric spacer on sidewalls of the opening; forming a gate dielectric on the exposed portion of the substrate; forming a functioning gate structure within the opening on the gate dielectric, wherein an upper surface of the functioning gate structure is a high-k dielectric capping layer; and forming contact vias through the interlevel dielectric layer to at least one of the source region and the drain region, wherein an etch that provides the opening for the contact via is selective to the high-k dielectric spacer and the high-k dielectric capping layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising:
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providing a first replacement gate structure within a first device region of a substrate and a second replacement gate structure within a second device region of the substrate, wherein the first device region comprises first source regions and first drain regions of a first conductivity type and the second device region comprises second source regions and second drain regions of a second conductivity type; forming an intralevel dielectric on the substrate having an upper surface that is coplanar with an upper surface of the first replacement gate structure and the second replacement gate structure; removing the first replacement gate structure and the second replacement gate structure to provide openings to a first exposed portion of the substrate in the first device region and a second exposed portion of the substrate in a second device region of the substrate; forming a high-k dielectric spacer on sidewalls of each of the openings to the first exposed portion of the substrate and the second exposed portion of the substrate; forming a gate dielectric on each of the first exposed portion and the second exposed portion of the substrate; forming a first work function metal layer on the gate dielectric that is present in the first device region and forming a second work function metal layer on the gate dielectric in the second device region of the substrate; forming a high-k dielectric capping layer over the first work function metal layer and the second work function metal layer; and forming contacts through the intralevel dielectric layer to at least one of the source region and the drain region, wherein an etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer. - View Dependent Claims (14, 15)
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16. A semiconductor device comprising:
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a gate structure that is composed of a gate conductor and a high-k gate dielectric layer, wherein the high-k gate dielectric layer is in contact with the base of the gate conductor and the sidewalls of the gate conductor; a high-k dielectric capping layer on an upper surface of the gate conductor; and source regions and drain regions in the substrate on opposing sides of the gate structure. - View Dependent Claims (17, 18, 19, 20)
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Specification