Multi-chip Package

• US 20120139068A1
• Filed: 11/28/2011
• Published: 06/07/2012
• Est. Priority Date: 11/26/2010
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Cambridge Silicon Radio Limited (Qualcomm, Inc.)
• Inventors: Stacey, Simon Jonathan
• Granted Patent: US 8,604,568 B2
• Time in Patent Office: Days
• US Class Current: 257/417
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 2203/0154 Moulding a cap over the MEMS device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73227 Wire and HDI connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/24 : solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method for forming a stacked integrated circuit package of primary dies on a carrier die, includes forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating carrier integrated circuits, the electrically conductive pillars providing electrical connections to said carrier integrated circuits; attaching primary dies to the active face of the carrier wafer, each supporting electrically conductive pillars at connection pads defined on an active face of the primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material; producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and singulating the carrier wafer to form stacked integrated circuit packages, each package comprising at least one primary die on a carrier die.

Claims

1. A method for forming a stacked integrated circuit package comprising one or more primary dies supported on a carrier die, the method comprising the steps of:

forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating a plurality of carrier integrated circuits, the electrically conductive pillars being configured to provide electrical connections to said carrier integrated circuits;

attaching a plurality of primary dies to the active face of the carrier wafer, each primary die supporting one or more electrically conductive pillars at connection pads defined on an active face of the primary die for providing electrical connections to a primary integrated circuit incorporated in the primary die;

encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material, the thickness of the insulating material being sufficient to cover the electrically conductive pillars of the carrier wafer and the plurality of primary dies;

producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and

singulating the carrier wafer so as to form a plurality of stacked integrated circuit packages, each stacked integrated circuit package comprising at least one primary die supported on a carrier die.

2. A method as claimed in claim 1, wherein the plurality of primary dies includes at least first and second primary dies, each die comprising a different integrated circuit, and the primary dies being arranged on the carrier wafer such that each stacked integrated circuit package comprises first and second primary dies.

3. A method as claimed in claim 1, wherein the electrically conductive pillars formed on the active face of the carrier wafer are arranged about the periphery of each carrier die of the wafer so as to provide at each carrier die an area free of electrically conductive pillars at which the at least one primary die can be attached.

4. A method as claimed in claim 1, wherein the step of forming electrically conductive pillars comprises electroplating copper pillars onto the carrier wafer.

5. A method as claimed in claim 1, wherein the electrically conductive pillars supported at the primary dies are formed during wafer level processing of the primary dies, prior to singulation of the primary dies.

6. A method as claimed in claim 1, wherein the relative heights of the electrically conductive pillars of the carrier dies and primary dies are selected such that, following the step of attaching the primary dies to the carrier wafer, the distal ends of the electrically conductive pillars of the carrier dies and of the primary dies are located at approximately the same perpendicular height above the carrier wafer.

7. A method as claimed in claim 1, wherein, prior to the step of removing a thickness of the insulating layer, the perpendicular height of the electrically conductive pillars of the carrier dies above the active surface of the carrier wafer is greater than the thickness of the at least one primary die plus the perpendicular height of the electrically conductive pillars of that primary die above the active surface of that primary die.

8. A method as claimed in claim 1, wherein the step of attaching a plurality of primary dies to the carrier wafer comprises one of:

bonding the primary dies to the active face of the carrier wafer by means of an adhesive die attach film; and

applying an epoxy resin between the primary dies and the carrier wafer, and curing the resin so as to bond the primary dies to the carrier wafer.

9. A method as claimed in claim 7, wherein the step of attaching a plurality of primary dies to the carrier wafer comprises one of:

bonding the primary dies to the active face of the carrier wafer by means of an adhesive die attach film; and

applying an epoxy resin between the primary dies and the carrier wafer, and curing the resin so as to bond the primary dies to the carrier wafer;

wherein the perpendicular height of the electrically conductive pillars of the carrier dies above the active surface of the carrier wafer is greater than the thickness of the at least one primary die plus the perpendicular height of the electrically conductive pillars of that primary die above the active surface of that primary die by approximately the thickness of the die attach film or epoxy resin by which the primary dies are attached to the carrier wafer.

10. A method as claimed in claim 1, further comprising, prior to the encapsulating step, forming a plurality of bonded wire electrical connections between connections of the primary integrated circuits incorporated in the plurality of primary dies and connections of the carrier integrated circuits incorporated in the carrier wafer.

11. A method as claimed in claim 10, wherein the connections of the primary and carrier integrated circuits are connection pads that do not support electrically conductive pillars.

12. A method as claimed in claim 10, wherein the height of the electrically conductive pillars on the primary dies is selected to be sufficiently large that the bonded wires are not exposed by the step of removing a thickness of the insulating layer.

13. A method as claimed in claim 1, wherein the encapsulating step comprises one of:

compression moulding the active face of the carrier wafer and the primary dies attached thereto with an epoxy resin and curing the resin so as to form an insulating epoxy polymer; and

covering the active face of the carrier wafer and the primary dies attached thereto with a polymer and curing the polymer so as to form a solid insulating polymer.

14. A method as claimed in claim 1, wherein the step of removing a thickness of the insulating layer comprises one or more of mechanical grinding, chemical polishing, plasma etching, and laser ablating material from the surface of the insulating layer.

15. A method as claimed in claim 1, wherein each carrier integrated circuit comprises a network of interconnects for conducting electrical signals between connections of the at least one primary integrated circuits, the network of interconnects optionally including one or more integrated passive devices.

16. A method as claimed in claim 1, further comprising, subsequent to the step of attaching a plurality of primary dies to the active face of the carrier wafer, attaching a secondary die to at least some of the primary dies, each secondary die supporting one or more electrically conductive pillars at connection pads defined on an active face of the secondary die for providing electrical connections to a secondary integrated circuit incorporated in the secondary die, wherein the secondary dies are arranged on the primary dies of the carrier wafer such that each stacked integrated circuit package comprises at least one secondary die.

17. A method as claimed in claim 16, wherein the electrically conductive pillars supported on the active face of the said at least some of the primary dies are arranged about the periphery of the primary die so as to provide an area free of electrically conductive pillars at which a secondary die can be attached, the secondary dies having a lesser planar area that the primary dies.

18. A method as claimed in claim 1, further comprising:

prior to the step of forming electrically conductive pillars on the carrier wafer, defining a microelectromechanical system on the active surface of each carrier die; and

prior to the step of attaching the plurality of primary dies to the carrier wafer, defining a cavity in at least some of the primary dies; and

performing the step of attaching the plurality of primary dies to the carrier wafer in respect of those primary dies having a cavity so defined by, under a vacuum or low pressure environment, sealing those primary dies over the said microelectromechanical systems defined on the active surface of the carrier wafer such that each microelectromechanical system is free to operate within the cavity defined in its respective primary die.

19. A method as claimed in claim 1, further comprising:

prior to the step of attaching the plurality of primary dies to the carrier wafer, defining a cavity in at least some of the primary dies and then defining a microelectromechanical system within the cavity so defined; and

performing the step of attaching the plurality of primary dies to the carrier wafer in respect of those primary dies having a cavity and microelectromechanical system by, under a vacuum or low pressure environment, sealing those primary dies to the active surface of the carrier wafer such that each microelectromechanical system is free to operate within the cavity defined in its respective primary die.

20. A method as claimed in claim 18, wherein the step of sealing the primary dies having a defined cavity comprises bonding those primary dies to the carrier wafer by glass frit bonding or metal eutectic bonding.

21. A method as claimed in claim 18, wherein each of the primary dies having a defined cavity incorporates a controller integrated circuit for the respective microelectromechanical system to be enclosed within that cavity.

22. A method as claimed in claim 18, wherein the step of defining a cavity in the at least some of the primary dies is performed at the wafer level by one or more of wet etching, plasma etching, and laser ablation.

23. A method as claimed in claim 18, wherein the step of defining a microelectromechanical system is performed by one or more of physical deposition, chemical deposition, lithography, diamond patterning, wet etching, and dry etching.

24. A method as claimed in claim 1, further comprising, prior to the step of singulating the carrier wafer, processing the wafer package in accordance with one or more wafer level processing techniques, including one or both of:

forming a redistribution layer so as to map said exposed electrically conductive pillars to a regular array of electrical contacts and/or form electrical connections between electrically conductive pillars of the carrier and primary dies; and

forming under-bump metallisation so as to provide an array of electrically conductive mounting points suitable for receiving solder balls.

25. A method as claimed in claim 24, wherein, subsequent to singulation of the wafer package so as to form a plurality of stacked integrated circuit packages, each stacked integrated circuit package is suitable for flip chip connection into a circuit.

26. A stacked integrated circuit package comprising a primary die incorporating a primary integrated circuit bonded to the active surface of a carrier die incorporating a carrier integrated circuit, the active surface of the carrier die and the primary die bonded thereto being encapsulated in a layer of insulating material, and each of the primary and carrier dies supporting a plurality of electrically conductive pillars each extending through said layer of insulating material from an electrical connection pad of the integrated circuit of the respective die to a redistribution layer configured so as to electrically map a ball or land grid array to the electrically conductive pillars.

27. A stacked integrated circuit package as claimed in claim 26, wherein the primary die includes one or more through-silicon-vias each arranged to provide an electrical connection between the integrated circuits of the primary and carrier dies.

28. A stacked integrated circuit package as claimed in claim 26, wherein the face of the primary die that is bonded to the carrier die includes a cavity enclosing a microelectromechanical system.

29. A stacked integrated circuit package as claimed in claim 28, wherein the microelectromechanical system is defined in the active surface of the carrier die or in the cavity of the primary die.

30. A stacked integrated circuit package as claimed in claim 28, wherein the primary integrated circuit incorporated in the primary die is a controller for the said microelectromechanical system.

31. A stacked integrated circuit package as claimed in claim 28, wherein the stacked integrated circuit package is a multi-axis accelerometer or gyroscope.