METHOD FOR FORMING ISOLATION TRENCHES

• US 20120139127A1
• Filed: 12/02/2011
• Published: 06/07/2012
• Est. Priority Date: 12/07/2010
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Beyne, Eric
• Granted Patent: US 8,742,590 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.

Claims

1. A method for providing at least one through silicon via interconnect structure, comprising:

providing a substrate comprising a substrate material having a first main surface;

etching, simultaneously, at least one through silicon via hole and at least one trench-like structure, the isolating trench-like structure surrounding the through silicon via hole and being separated from the through silicon via hole by a remaining substrate material;

thereafter

thereafter, depositing a dielectric liner, whereby sidewalls of the etched through silicon via hole are smoothed and whereby an opening of the isolating trench-like structure is pinched off at the first main surface of the substrate, thereby creating a hollow trench-like structure with at least one airgap in the hollow trench-like structure; and

thereafter

depositing a conductive material in the through silicon via hole, whereby a through silicon via interconnect structure surrounded by the hollow trench-like structure is provided.

2. The method according to claim 1, wherein the substrate is a silicon wafer having active devices on its first main surface material, wherein the active devices are produced during a preceding front end of line processing.

3. The method according to claim 1, wherein etching, simultaneously, at least one through silicon via hole and at least one isolating trench-like structure is performed using an aspect-ratio-dependent etching, such that the isolating trench-like structure has a trench width of from 100 nm to 500 nm and the through silicon via hole has a diameter or width of from 2 μ

m to 20 μ

m and the isolating trench-like structure has a depth of from ⅕

to ⅔

of a depth of the through silicon via hole.

4. The method according to claim 3, wherein the aspect-ratio-dependent etching is a pulsed etching comprising alternating steps of isotropic etching and passivation.

5. The method according to claim 4, wherein the isotropic etching is a SF₆ based plasma etching and wherein the passivation is a C4F8 based plasma passivation.

6. The method according to claim 4, wherein the isotropic etching and/or the passivation comprises using oxygen and/or at least one inert gas.

7. The method according to claim 1, wherein the deposited liner is a tetraethyl orthosilicate liner.

8. The method according to claim 1, wherein depositing a conductive material in the through silicon via hole is performed using an electrochemical deposition technique or a chemical vapor deposition technique, and wherein the conductive material comprises at least one material selected from the group consisting of a metal, copper, nickel, tungsten, a metal alloy, an implanted semiconductor, a conductive silicon, a conducting polymer, and carbon nanotubes.

9. The method according to claim 1, further comprising, after depositing a conductive material in the through silicon via hole, at least one of a planarization of the conductive material to remove an overburden of conductive material on horizontal parts of the substrate or a thermal anneal to initiate grain growth of a metal, wherein the conductive material comprises the metal.

10. The method according to claim 1, wherein the at least one through silicon via hole has a diameter of from 2 μ

m to 20 μ

m and the isolating trench-like structure has a trench width smaller than 1000 nm.

11. The method according to claim 1, further comprising, after depositing a conductive material in the through silicon via hole, providing metal contacts onto the through silicon via interconnect structure and forming a plurality of back-end-of-line interconnect layers.

12. The method according to claim 1, further comprising thinning a backside of the substrate using a mechanical operation to open the through silicon via interconnect structure from the backside, whereby a three-dimensional through silicon via interconnect structure is formed.

13. The method according to claim 12, further comprising providing the through silicon via interconnect structure with a solder ball or solder bump.

14. A substrate comprising at least one through silicon via interconnect structure prepared by the method according to claim 1, wherein the through silicon via interconnect structure is a three-dimensional through silicon via interconnect structure surrounded by the hollow trench-like structure.

15. A three-dimensional stacked semiconductor device comprising a substrate according to claim 14.