SEMICONDUCTOR DEVICE AND METHOD OF SENSING DATA OF THE SEMICONDUCTOR DEVICE

• US 20120140545A1
• Filed: 09/15/2011
• Published: 06/07/2012
• Est. Priority Date: 12/07/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ho-jung, Shin, Jai-kwang, Choi, Hyun-sik, Jeong, Hyung-su
• Granted Patent: US 8,503,220 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

Claims

1. A semiconductor device comprising:

a memory cell array including at least one memory cell disposed in a region at which at least one bit line and at least one word line cross; and

a sensing unit configured to sense data stored in the at least one memory cell, the sensing unit including a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

2. The semiconductor deice of claim 1, wherein the sensing unit further includes

a sense amplifying unit configured to generate a sense result based on a voltage of the sensing line and a reference voltage.

3. The semiconductor device of claim 2, wherein the sensing unit further includes a precharging unit configured to precharge the sensing line to a first precharge voltage according to a precharge enable signal.

4. The semiconductor device of claim 3, wherein the semiconductor device is configured such that the control signal has a first voltage level in a precharge period in which the precharge enable signal is activated, and has a second voltage level less than the first voltage level in a develop period in which a develop enable signal is activated.

5. The semiconductor device of claim 4, wherein the at least one memory cell is a multi-level cell (MLC) capable of storing multi-level data, and

wherein the semiconductor device is configured such that the second voltage level corresponds to a level of data to be sensed from among the multi-level data.

6. The semiconductor device of claim 4, wherein the at least one memory cell is a multi-level resistive memory cell capable of storing multi-level data respectively corresponding to a plurality of resistance levels, and

wherein the semiconductor device is configured such that the second voltage level is proportional to a resistance level of data to be sensed from among the multi-level data.

7. The semiconductor device of claim 4, wherein the connection control unit includes a clamping unit that is connected between the at least one bit line and the sensing line, and the clamping unit is configured to clamp the at least one bit line to a constant voltage level according to the control signal.

8. The semiconductor device of claim 7, wherein the clamping unit includes a switching device that is configured to be activated in response to the control signal, connecting the at least one bit line and the sensing line.

9. The semiconductor device of claim 8, wherein the connection control unit is configured to connect the at least one bit line and the sensing line in the precharge period, and the at least one bit line is precharged to a second precharge voltage corresponding to a difference between the first voltage level and a threshold voltage of the switching device.

10. The semiconductor device of claim 8, wherein the connection control unit is configured to connect the at least one bit line and the sensing line if the voltage level of the at least one bit line is less than a difference between the second voltage level and the threshold voltage of the switching device in the develop period.

11. The semiconductor device of claim 10, wherein the sensing unit is configured such that, if the at least one bit line and the sensing line are connected, a voltage level of the sensing line is decreased to the voltage level of the at least one bit line, and

wherein the sense amplifying unit senses the at least one memory cell as an ON cell.

12. The semiconductor device of claim 8, wherein the connection control unit configured such that, if the voltage level of the at least one bit line is greater than a difference between the second voltage level and the threshold voltage of the switching device in the develop period, the connection control unit does not connect the at least one bit line and the sensing line.

13. The semiconductor device of claim 12, wherein, the sensing unit is configured such that, when the at least one bit line and the sensing line are not connected, a voltage level of the sensing line is maintained at the first precharge voltage, and

wherein the sense amplifying unit senses the at least one memory cell as an OFF cell.

14. The semiconductor device of claim 8, wherein the connection control unit further includes at least two discharge devices each connected to terminals of the switching device, and the two discharge devices are configured to discharge a voltage of the at least one bit line and the voltage of the sensing line in a discharge period in which a discharge enable signal is activated.

15. The semiconductor device of claim 8, wherein the connection control unit further includes:

a temperature sensing unit configured to sense a temperature variation of a surrounding temperature of the semiconductor device; and

a control signal providing unit configured to adjust a voltage level of the control signal according to the sensed temperature variation so as to compensate for the a variation of a threshold voltage of the switching device according to the variation of the surrounding temperature, and configured to provide the switching device with the control signal having the adjusted voltage level.

16. The semiconductor device of claim 1, wherein the semiconductor device is configured to sense data stored in the at least one memory cell without using a reference current provided by a reference cell.

18. The method of claim 16, further comprising:

precharging the at least one bit line according to a precharge enable signal; and

generating a sensing result based on a voltage of the sensing line and a reference voltage.

19. The method of claim 18, wherein the control signal has a first voltage level in a precharge period in which the precharge enable signal is activated, and has a second voltage level less than the first voltage level in a develop period in which a develop enable signal is activated.

20. The method of claim 19, wherein the at least one memory cell is a multi-level cell (MLC) capable of storing multi-level data, and

wherein the second voltage level corresponds to a level of data to be sensed from among the multi-level data.

21. The method of claim 19, wherein the precharging of the at least one bit line includes:

precharging the sensing line to a first precharge voltage according to the precharge enable signal; and

precharging the at least one bit line to a second precharge voltage by connecting the sensing line and the at least one bit line,

wherein the second precharge voltage corresponds to a difference between the first voltage level and a threshold voltage.

22. The method of claim 19, wherein the controlling of the connection includes

connecting the at least one bit line and the sensing line if the voltage level of the at least one bit line is less than a difference between the second voltage level and a threshold voltage in the develop period.

23. The method of claim 22, wherein, if the at least one bit line and the sensing line are connected, a voltage level of the sensing line is decreased to the voltage level of the at least one bit line, and

wherein the at least one memory cell is sensed as an ON cell.

24. The method of claim 19, wherein the controlling of the connection includes preventing the connection of the at least one bit line and the sensing line if the voltage level of the at least one bit line is greater than a difference between the second voltage level and a threshold voltage in the develop period.

25. The method of claim 24, wherein, if the at least one bit line and the sensing line are not connected, a voltage level of the sensing line is not decreased to the voltage level of the at least one bit line, and

wherein the at least one memory cell is sensed as an OFF cell.

17. A method of sensing data stored in at least one memory cell in a semiconductor device comprising the at least one memory cell disposed in a region at which at least one bit line and at least one word line, the method comprising:

controlling a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

26. The method of claim 17, further comprising discharging a voltage of the at least one bit line and the voltage of the sensing line in a discharge period in which a discharge enable signal is activated.

27. The method of claim 17, further comprising:

sensing a temperature variation of the semiconductor device;

adjusting a voltage level of the control signal according to the sensed temperature variation; and

providing the control signal having the adjusted voltage level.