NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20120140549A1
• Filed: 02/16/2012
• Published: 06/07/2012
• Est. Priority Date: 04/25/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAEJIMA, Hiroshi
• Granted Patent: US 8,432,722 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch said variable resistor;

a column control circuit operative to, during verify read from said memory cell, select a certain at least one of said second lines and charge the selected second line to a certain charged-level; and

a row control circuit operative to, during verify read from said memory cell, select a certain at least one of said first lines, supply to the selected first line a certain selected first line voltage, and supply to unselected first lines a blocking voltage higher than said charged-level and said selected first line voltage,

wherein said column control circuit changes a clamp voltage for limiting said charged-level in response to a temperature.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said column control circuit changes said clamp voltage to compensate for the temperature characteristic of said first non-ohmic element.

3. The nonvolatile semiconductor memory device according to claim 1, wherein said column control circuit includes a sense amplifier connected to said second line via a clamp transistor having a gate supplied with said clamp voltage and operative to read out data from said memory cell.

4. The nonvolatile semiconductor memory device according to claim 3, wherein said clamp voltage is a voltage which enables said clamp transistor to transfer at least an assumable highest value of said charged-level.

5. The nonvolatile semiconductor memory device according to claim 3,

wherein said sense amplifier includes a current source circuit connected to said clamp transistor via a sense node, and

said current source circuit includes a transistor connected to said clamp transistor via said sense node.

6. The nonvolatile semiconductor memory device according to claim 1,

wherein said column control circuit includes a clamp voltage generator circuit operative to generate said clamp voltage.

7. The nonvolatile semiconductor memory device according to claim 5,

wherein said transistor of said current source circuit includes a gate supplied with a bias voltage which changes according to data to be read out.

8. The nonvolatile semiconductor memory device according to claim 7,

wherein, during said verify read and after said bias voltage is supplied to said transistor of said current source circuit, said clamp voltage is supplied to said clamp transistor.

9. The nonvolatile semiconductor memory device according to claim 3,

wherein, during verify read from said memory cell and after said selected first line voltage is supplied to said selected first line and said blocking voltage is supplied to said unselected first lines, said clamp voltage is supplied to said clamp transistor.

10. The nonvolatile semiconductor memory device according to claim 7,

wherein, during verify read from said memory cell and after said selected first line voltage is supplied to said selected first line and said blocking voltage is supplied to said unselected first lines, said clamp voltage is supplied to said clamp transistor.

11. The nonvolatile semiconductor memory device according to claim 10,

wherein, after said bias voltage is supplied to said transistor of said current source circuit, said clamp voltage is supplied to said clamp transistor.

12. The nonvolatile semiconductor memory device according to claim 3,

wherein said column control circuit, during verify read from said memory cell, sets unselected second lines to a floating state.

13. The nonvolatile semiconductor memory device according to claim 7,

wherein said column control circuit, during verify read from said memory cell, sets unselected second lines to a floating state.

14. The nonvolatile semiconductor memory device according to claim 12,

wherein, during verify read from said memory cell and after said selected first line voltage is supplied to said selected first line and said blocking voltage is supplied to said unselected first lines, said clamp voltage is supplied to said clamp transistor.

15. The nonvolatile semiconductor memory device according to claim 13,

wherein, during verify read from said memory cell and after said selected first line voltage is supplied to said selected first line and said blocking voltage is supplied to said unselected first lines, said clamp voltage is supplied to said clamp transistor.

16. The nonvolatile semiconductor memory device according to claim 15,

wherein, after said bias voltage is supplied to said transistor of said current source circuit, said clamp voltage is supplied to said clamp transistor.