MEMORY CELL OPERATION

• US 20120140569A1
• Filed: 02/14/2012
• Published: 06/07/2012
• Est. Priority Date: 10/22/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Aritome, Seiichi
• Granted Patent: US 8,787,090 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.

Claims

1. A method for operating an array of memory cells, the method comprising:

determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state; and

adjusting, from an initial level to an adjusted level, at least one operating parameter associated with programming the group of memory cells at least partially based on the quantity of erase pulses.

2. The method of claim 1, wherein the method includes programming the group of memory cells using the adjusted level for the at least one operating parameter.

3. The method of claim 1, wherein adjusting includes:

maintaining the at least one operating parameter at the initial level when the quantity of erase pulses is below a first quantity;

adjusting one or more of the at least one operating parameter to the adjusted level when the quantity of erase pulses is between the first quantity and a second quantity; and

adjusting one or more of the at least one operating parameter to a different adjusted level when the quantity of erase pulses is greater than the second quantity.

4. The method of claim 1, wherein the method includes determining the quantity of erase pulses by counting the quantity of erase pulses.

5. The method of claim 1, wherein the at least one operating parameter includes at least one operating voltage, and wherein adjusting includes decreasing a magnitude of the at least one operating voltage.

6. The method of claim 1, wherein adjusting includes decreasing the magnitude of at least one of:

a program start voltage;

a program step voltage; and

a pass-through voltage.

7. The method of claim 1, wherein adjusting includes increasing at least one operating voltage associated with programming the group of memory cells.

8. The method of claim 7, wherein increasing at least one operating voltage includes increasing a program verify voltage associated with programming the group of memory cells.

9. A memory device comprising:

an array of memory cells; and

a controller coupled to the array and configured to;

track a quantity of erase pulses used to place a number of memory cells of the array in an erased state; and

adjust at least one operating parameter associated with programming the number of memory cells at a number of particular intervals based, at least partially, on the quantity of erase pulses.

10. The memory device of claim 9, wherein the controller is further configured to program the number of memory cells using at least one adjusted operating voltage.

11. The memory device of claim 9, wherein the controller is configured to:

count the quantity of erase pulses used to place the number of memory cells in the erased state;

identify a range of program/erase processing cycles corresponding to the quantity of erase pulses; and

adjust a number of operating parameters associated with the range.

12. The memory device of claim 9, wherein the at least one operating parameter adjusted by the controller includes a programming start voltage and a programming step voltage.

13. The memory device of claim 9, wherein the controller is configured to:

maintain the at least one operating parameter at an initial level when the quantity of erase pulses is at or below a first quantity; and

adjust the at least one operating parameter when the quantity of erase pulses is at or exceeds each of a number of thresholds.

14. The memory device of claim 9, wherein the number of thresholds is at least two and wherein the controller is configured to:

adjust the at least one operating parameter to a first adjusted level when the quantity of erase pulses reaches or exceeds a first threshold; and

adjust the at least one operating parameter to second adjusted level when the quantity of erase pulses reaches or exceeds a second threshold.

15. The memory device of claim 14, wherein the second threshold is greater than the first threshold.

16. A method for operating an array of memory cells, the method comprising:

counting a quantity of erase pulses used to place a number of memory cells of the array in an erased state; and

changing, from an initial voltage to an adjusted voltage, at least one operating voltage associated with programming the number of memory based, at least partially, on the quantity of erase pulses.

17. The method of claim 16, wherein changing includes decreasing a programming start voltage and decreasing a pass-through voltage associated with programming the number of memory cells.

18. The method of claim 16, including:

estimating a quantity of program/erase cycles performed on the number of memory cells based on the quantity of erase pulses used to place the number of memory cells in the erased state; and

changing the at least one operating voltage from the initial voltage to the adjusted voltage when the quantity of program/erase cycles reaches or exceeds a threshold quantity.

19. The method of claim 16, including adjusting a maximum erase pulse magnitude associated with erasing the number of memory cells based on the quantity of erase pulses.

20. A memory device comprising:

an array of memory cells; and

a controller coupled to the array and configured to;

determine a quantity of erase pulses used to place a number of memory cells of the array in an erased state; and

adjust, from an initial level to one of at least two different adjusted levels, at least one operating parameter associated with programming the number of memory cells based, at least partially, on the quantity of erase pulses;

wherein a first of the at least two different adjusted levels corresponds to a first threshold quantity of erase pulses and a second of the at least two different adjusted levels corresponds to a second threshold quantity of erase pulses.