METHOD FOR ESTIMATING THE LIFESPAN OF A DEEP-SUB-MICRON INTEGRATED ELECTRONIC CIRCUIT

• US 20120143557A1
• Filed: 06/30/2010
• Published: 06/07/2012
• Est. Priority Date: 07/01/2009
• Status: Active Grant

• Current Assignee: European Aeronautic Defence and Space Company EADS France (Airbus SE)
• Original Assignee: European Aeronautic Defence and Space Company EADS France (Airbus SE)
• Inventors: Foucher, Bruno, Moliere, Florian
• Granted Patent: US 9,058,574 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling

Abstract

A large range of commercial VLSI Deep Submicron circuits are used in aeronautics for designs of electronic cards. Due to miniaturization, a continually increasing level of integration and the use of new materials in the foundries, the main failure mechanisms change whilst other ones appear. The lifetimes linked to these failure mechanisms are suspected of being shorter and shorter, so that predicting the lifetime becomes a significant challenge for the reliability of Deep Submicron (DSM) semiconductors. A new approach is proposed here, based on analyzing the technology so as to determine the potential risks to reliability with respect to the specific use of DSM components for avionics applications.

Claims

1. Method for estimating the lifetime (TTF_APPLI) of a deep-submicron-generation integrated electronic component, linked to a wear mechanism occurring in previously defined special conditions of use, said component being of a deep submicron type, with very large-scale integration (VLSI), commercially available off the shelf,

characterized in that it is assumed that the same sample population always experiences a failure due to:

the most predominant failure mechanism, during the period of useful life, described by an exponential law,

the most critical wear mechanism, represented by a Weibull distribution at the end of the previous period,

and in that the method comprises the following steps;

Step 101—

of receiving and storing predefined elements of technical information about the component, in particular the power supply voltage(s), technological data (node, FEOL and BEOL description), the technical description of the encapsulation and the addressing data for the component,

Step 106—

of analyzing the component'"'"'s sensitivity with regard to specific conditions of use,

Step 116—

of selecting the most critical bottom of the bath and wear mechanisms, and associated accelerated tests.

2. Method according to claim 1, characterized in that it comprises, in addition, steps:

Step 111—

of calculating an estimated lifetime for the component in test conditions (TTF_TEST),

Step 112—

of determining an acceleration factor used for analyzing the results of at least one accelerated test of the component.

3. Method according to claim 1, characterized in that it comprises, in addition, a step:

Step 108—

of acquiring and storing the results of at least one accelerated test of the component'"'"'s lifetime, if such test results are not otherwise available;

the type of test is chosen according to a mechanism of failure by wear.

4. Method according to claim 1, characterized in that it comprises, in addition, a step:

Step 103—

of studying the component using a process of reverse engineering, so as to determine, in particular, its theoretical failure rate (A).

5. Method according to claim 1, characterized in that it comprises, in addition, a step:

Step 105—

of establishing an identity card for the component according to a series of predefined criteria (technology, failure mechanisms inherent in the technology, etc.).

6. Method according to claim 1, characterized in that it comprises, in addition, a step:

Step 102—

of characterizing environmental data corresponding to the specific conditions of use planned for the component, in particular the electrical and thermal mission profile.

7. Method according to claim 1, characterized in that it comprises, in addition, a step:

Step 110—

of identifying failure mechanisms observed at the time of failures under test conditions.

8. Method according to claim 1, characterized in that it comprises, in addition, a step:

Step 109—

of calculating the observed failure rate λ

_TEST under test conditions.

9. Method according to claim 2, characterized in that, in step 111:

the probability of failures is described by a bimodal distribution (Eq.

     1) in which A_TEST is the failure rate under test conditions, TFT<sub>TEST—

R %</sub> the mean value of the time to failure for components that have survived after t=t_TEST and β

the Weibull slope of the wear mechanism;

10. Method according to claim 9, characterized in that it comprises, in addition, a step:

Step 113, 114—

of calculating the effective failure rates λ

_APPLI and lifetime TTF_APPLI in use, according to the appropriate acceleration factor AF, from the failure rate λ

_TEST and lifetime TTF_TEST measured during the accelerated tests, by applying the formulas;

11. Method according to claim 2, characterized in that it comprises, in addition, a step:

Step 108—

of acquiring and storing the results of at least one accelerated test of the component'"'"'s lifetime, if such test results are not otherwise available;

the type of test is chosen according to a mechanism of failure by wear.

12. Method according to claim 2, characterized in that it comprises, in addition, a step:

Step 103—

of studying the component using a process of reverse engineering, so as to determine, in particular, its theoretical failure rate (A).

13. Method according to claim 2, characterized in that it comprises, in addition, a step:

Step 105—

of establishing an identity card for the component according to a series of predefined criteria (technology, failure mechanisms inherent in the technology, etc.).

14. Method according to claim 2, characterized in that it comprises, in addition, a step:

Step 102—

of characterizing environmental data corresponding to the specific conditions of use planned for the component, in particular the electrical and thermal mission profile.

15. Method according to claim 2, characterized in that it comprises, in addition, a step:

Step 110—

of identifying failure mechanisms observed at the time of failures under test conditions.

16. Method according to claim 2, characterized in that it comprises, in addition, a step:

Step 109—

of calculating the observed failure rate λ

_TEST under test conditions.