Transferring Power and Speed from a Lock Requester to a Lock Holder on a System with Multiple Processors

• US 20120144218A1
• Filed: 12/03/2010
• Published: 06/07/2012
• Est. Priority Date: 12/03/2010
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brey, Thomas M., Rawson, Freeman L. III
• Application Number:
  US12/959,804
• Publication Number:
  US 20120144218A1
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power is allocated between processors in a multiprocessor system. A request to acquire a lock is received from a first thread executing on a first processor. Responsive to receiving the request to acquire a lock, determination is made as to whether a second thread has acquired the lock. Responsive to determining that the second thread has acquired the lock, an original frequency of the first thread executing on the first processor and an operating frequency of the second thread executing on the second processor is identified. The operating frequency of the second thread executing on the second processor is then altered based on the original frequency of the first thread executing on the first processor. When the second thread releases the lock, the spinning thread with the highest original frequency acquires the lock.

Claims

1. A computer implemented method for allocating power between processors in a multiprocessor system, the method comprising:

receiving a request to acquire a lock from a first thread executing on a first processor;

responsive to receiving the request to acquire a lock, determining whether a second thread has acquired the lock;

responsive to determining that the second thread has acquired the lock, identifying an original frequency of the first thread executing on the first processor and identifying an operating frequency of the second thread executing on the second processor; and

altering the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor.

2. The computer implemented method of claim 1, further comprising:

setting an operating frequency of the first thread executing on the first processor equal to a low processor frequency associated with a low power setting, wherein the first thread is waiting to acquire the lock.

3. The computer implemented method of claim 1, further comprising:

determining whether the original frequency of the first thread executing on the first processor is greater than the operating frequency of the second thread executing on the second processor;

responsive to determining that the original frequency of the first thread is greater than the operating frequency of the second thread, altering the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor, wherein altering the operating frequency of the second thread further comprises;

setting the operating frequency of the second thread executing on the second processor equal to the original frequency of the first thread executing on the first processor.

4. The computer implemented method of claim 2, wherein the step of altering the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor further comprises:

augmenting the operating frequency of the second thread executing on the second processor by an amount equal to the difference between the original frequency of the first thread and the operating frequency of the first thread.

5. The computer implemented method of claim 4, further comprising:

receiving a second request to acquire the lock from a third thread executing on a third processor;

setting an operating frequency of the third thread executing on the third processor to the low processor frequency associated with the low power setting;

determining whether an original frequency of the third thread executing on the third processor is greater than the operating frequency of the second thread executing on the second processor;

responsive to determining that the original frequency of the third thread is greater than the operating frequency of the second thread, augmenting the operating frequency of the second thread executing on the second processor by an amount equal to the difference between an original frequency of the third thread and the operating frequency of the first thread.

6. The computer implemented method of claim 5, wherein the operating frequency of the second thread executing on the second processor is determined by the formula:

7. The computer implemented method of claim 2, further comprising:

releasing the lock by the second thread executing on the second processor;

setting the operating frequency of the second thread executing on the second processor equal to an original frequency of the second thread executing on the second processor; and

setting the operating frequency of the first thread executing on the first processor equal to the original frequency of the first thread executing on the first processor.

8. The computer implemented method of claim 5 further comprising:

releasing the lock by the second thread executing on the second processor;

determining whether the original frequency of the first thread executing on the first processor is greater than the original frequency of the third thread executing on the third processor;

responsive to determining that the original frequency of the first thread is greater than the original frequency of the third thread, granting the lock to the first thread; and

altering the operating frequency of the first thread executing on the first processor based on the original frequency of the third thread executing on the third processor.

9. A computer storage type medium having computer usable instructions encoded thereon for allocating power between processors in a multiprocessor system, the computer usable instructions comprising:

instructions for receiving a request to acquire a lock from a first thread executing on a first processor;

instructions, responsive to receiving the request to acquire a lock, for determining whether a second thread has acquired the lock;

instructions, responsive to determining that the second thread has acquired the lock, for identifying an original frequency of the first thread executing on the first processor and identifying an operating frequency of the second thread executing on the second processor; and

instructions for altering the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor.

10. The computer storage type medium of claim 9, further comprising:

instructions for setting an operating frequency of the first thread executing on the first processor equal to a low processor frequency associated with a low power setting, wherein the first thread is waiting to acquire the lock.

11. The computer storage type medium of claim 9, the computer usable instructions further comprising:

instructions for determining whether the original frequency of the first thread executing on the first processor is greater than the operating frequency of the second thread executing on the second processor;

instructions, responsive to determining that the original frequency of the first thread is greater than the operating frequency of the second thread, for altering the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor, wherein altering the operating frequency of the second thread further comprises;

instructions for setting the operating frequency of the second thread executing on the second processor equal to the original frequency of the first thread executing on the first processor.

12. The computer storage type medium of claim 10, wherein the instructions for altering the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor further comprises:

instructions for augmenting the operating frequency of the second thread executing on the second processor by an amount equal to the difference between the original frequency of the first thread and the operating frequency of the first thread.

13. The computer storage type medium of claim 12, the computer usable instructions further comprising:

instructions for receiving a second request to acquire the lock from a third thread executing on a third processor;

instructions for setting an operating frequency of the third thread executing on the third processor to the low processor frequency associated with the low power setting;

instructions for determining whether an original frequency of the third thread executing on the third processor is greater than the operating frequency of the second thread executing on the second processor;

instructions, responsive to determining that the original frequency of the third thread is greater than the operating frequency of the second thread, for augmenting the operating frequency of the second thread executing on the second processor by an amount equal to the difference between an original frequency of the third thread and the operating frequency of the first thread.

14. The computer storage type medium of claim 13, wherein the operating frequency of the second thread executing on the second processor is determined by the formula:

15. The computer storage type medium of claim 9, the computer usable instructions further comprising:

instructions for releasing the lock by the second thread executing on the second processor;

instructions for setting the operating frequency of the second thread executing on the second processor equal to an original frequency of the second thread executing on the second processor; and

instructions for setting the operating frequency of the first thread executing on the first processor equal to the original frequency of the first thread executing on the first processor.

16. The computer storage type medium of claim 13, the computer usable instructions further comprising:

instructions for releasing the lock by the second thread executing on the second processor;

instructions for determining whether the original frequency of the first thread executing on the first processor is greater than the original frequency of the third thread executing on the third processor;

instructions, responsive to determining that the original frequency of the first thread is greater than the original frequency of the third thread, for granting the lock to the first thread; and

instructions for altering the operating frequency of the first thread executing on the first processor based on the original frequency of the third thread executing on the third processor.

17. A data processing system comprising:

a storage having computer usable instructions encoded thereon for allocating power between processors in a multiprocessor system;

a bus connecting the storage to a processor; and

a processor, wherein the processor executes the computer usable instructions;

to receive a request to acquire a lock from a first thread executing on a first processor;

responsive to receiving the request to acquire a lock, to determine whether a second thread has acquired the lock;

responsive to determining that the second thread has acquired the lock, to identify an original frequency of the first thread executing on the first processor and identifying an operating frequency of the second thread executing on the second processor; and

to alter the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor.

18. The data processing system of claim 17, wherein the processor further executes the computer usable instructions:

to set an operating frequency of the first thread executing on the first processor equal to a low processor frequency associated with a low power setting, wherein the first thread is waiting to acquire the lock.

19. The data processing system of claim 17, wherein the processor further executes the computer usable instructions:

to determine whether the original frequency of the first thread executing on the first processor is greater than the operating frequency of the second thread executing on the second processor;

responsive to determining that the original frequency of the first thread is greater than the operating frequency of the second thread, to alter the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor, wherein the processor further executes the computer usable instructions to alter the operating frequency of the second thread further comprises the processor further executes the computer usable instructions to set the operating frequency of the second thread executing on the second processor equal to the original frequency of the first thread executing on the first processor.

20. The data processing system of claim 18, wherein the processor further executes the computer usable instructions to alter the operating frequency of the second thread executing on the second processor based on the original frequency of the first thread executing on the first processor further comprises the processor further executes the computer usable instructions to augment the operating frequency of the second thread executing on the second processor by an amount equal to the difference between the original frequency of the first thread and the operating frequency of the first thread.

21. The data processing system of claim 20, wherein the processor further executes the computer usable instructions:

to receive a second request to acquire the lock from a third thread executing on a third processor;

to set an operating frequency of the third thread executing on the third processor to the low processor frequency associated with the low power setting;

to determine whether an original frequency of the third thread executing on the third processor is greater than the operating frequency of the second thread executing on the second processor; and

responsive to determining that the original frequency of the third thread is greater than the operating frequency of the second thread, to augment the operating frequency of the second thread executing on the second processor by an amount equal to the difference between an original frequency of the third thread and the operating frequency of the first thread.

22. The data processing system of claim 18, wherein the processor further executes the computer usable instructions:

to release the lock by the second thread executing on the second processor;

to set the operating frequency of the second thread executing on the second processor equal to an original frequency of the second thread executing on the second processor; and

to set the operating frequency of the first thread executing on the first processor equal to the original frequency of the first thread executing on the first processor.

23. The data processing system of claim 21, wherein the processor further executes the computer usable instructions:

to the lock by the second thread executing on the second processor;

to determine whether the original frequency of the first thread executing on the first processor is greater than the original frequency of the third thread executing on the third processor;

responsive to determining that the original frequency of the first thread is greater than the original frequency of the third thread, to grant the lock to the first thread; and

to alter the operating frequency of the first thread executing on the first processor based on the original frequency of the third thread executing on the third processor.