STORAGE CONTROL APPARATUS AND STORAGE CONTROL METHOD

• US 20120144252A1
• Filed: 12/01/2010
• Published: 06/07/2012
• Est. Priority Date: 12/01/2010
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Takada, Masanori
• Granted Patent: US 8,438,429 B2
• Time in Patent Office: Days
• US Class Current: 714/702
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2211/1035 Keeping track, i.e. keeping track of data and parity changes

Abstract

A first memory area and a second memory area are provided. The first (second) memory area is provided with at least one first (second) memory module group, each of the first (second) memory module group is provided with at least one first (second) memory module, and each of the first (second) memory module is provided with a plurality of memory chip. In the case in which an error chip that is a memory chip that is provided with an error is in the first memory module, a first memory module group that is provided with the error chip is not managed as a memory module group that cannot be used even if there is a possibility that an error of the first data element is mis-corrected based on the error detecting code of the first kind. In the case in which an error chip is in the second memory module, a second memory module group that is provided with the error chip is not managed as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind.

Claims

1. A storage control apparatus comprising:

a first memory area;

a second memory area; and

a controller that is coupled to the first memory area and the second memory area, where in the case in which the controller writes the first data to the first memory area, the controller adds an error detecting code of the first kind to a first data element that is an element of the first data and then writes the first data to the first memory area, and in the case in which the controller writes the second data to the second memory area, the controller adds an error detecting code of the first kind to a second data element that is an element of the second data and then writes the second data to the second memory area,

wherein the first memory area is provided with at least one first memory module group, each of the first memory module group is provided with at least one first memory module, and each of the first memory module is provided with a plurality of memory chip, the second memory area is provided with at least one second memory module group, each of the second memory module group is provided with at least one second memory module, and each of the second memory module is provided with a plurality of memory chip,

(A) in the case in which an error chip that is a memory chip that is provided with an error is a memory chip in the first memory module, the controller does not control a first memory module group that is provided with the error chip as a memory module group that cannot be used even if there is a possibility that an error of the first data element is mis-corrected based on the error detecting code of the first kind, and

(B) in the case in which an error chip that is a memory chip that is provided with an error is a memory chip in the second memory module, the controller controls a second memory module group that is provided with the error chip as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind.

2. A storage control apparatus according to claim 1, further comprising:

a first communication interface that is coupled to a host computer; and

a second communication interface that is coupled to a physical storage device,

wherein the controller is coupled to the first communication interface and the second communication interface, and executes the following step (W) or (R);

(W) receiving a write command and the write target data from the host computer via the first communication interface, adding the error detecting code of the second kind to the write target data, and writing the write target data to the physical storage device via the second communication interface; and

(R) receiving a read command from the host computer via the first communication interface, reading the read target data from the physical storage device via the second communication interface, and transmitting the read target data to the host computer via the first communication interface, and

wherein the first data is a set of the user data that is the write target data or the read target data and the error detecting code of the second kind that is added to the user data, and

the second data is the control data to which an error detecting code is not added.

3. A storage control apparatus according to claim 2, wherein:

the error detecting code of the first kind is an ECC (Error Correcting Code), and

the error detecting code of the second kind is a CRC (Cyclic Redundancy Check).

4. A storage control apparatus according to claim 1, wherein:

the number of memory chips that configure the second memory module group is larger than that of memory chips that configure the first memory module group, and

the number of data transfer cycles from the controller to the second memory module group is shorter than the number of data transfer cycles from the controller to the first memory module group.

5. A storage control apparatus according to claim 4, wherein:

the number of memory chips that configure the second memory module group is N times as much as that of memory chips that configure the first memory module group (N is a natural number larger than

     1), and

the number of data transfer cycles from the controller to the second memory module group is 1/N times as short as than the number of data transfer cycles from the controller to the first memory module group.

6. A storage control apparatus according to claim 1, wherein:

in the (B), in the case in which one second memory module is provided with at least one error chip, the controller disables a second memory module group that is provided with the second memory module.

7. A storage control apparatus according to claim 6, wherein:

there is a multiplexed second memory module group in the second memory area,

in the case in which the controller writes the second data element into the second memory area, the controller writes the second data element and an error detecting code of the first kind that is added to the second data element into the multiplexed second memory module group, and

one of the multiplexed second memory module group is disabled in the (B), and a second memory module group that is not disabled among the multiplexed second memory module group is managed as a memory module group that can be used.

8. A storage control apparatus according to claim 7, wherein:

a storage capacity of the second memory module group is smaller than that of the first memory module group.

9. A storage control apparatus according to claim 1, wherein:

a maximum data transfer length from the controller to the second memory module group is shorter than a maximum data transfer length from the controller to the first memory module group.

10. A storage control apparatus according to claim 1, wherein:

a storage capacity of the second memory module group is smaller than that of the first memory module group.

11. A storage control apparatus according to claim 1, wherein:

a maximum size of data that can be read or written in a unit time to the second memory module group is smaller than a maximum size of data that can be read or written in a unit time to the first memory module group.

12. A storage control apparatus according to claim 1, wherein:

the first data is a set of data and an error detecting code of the second kind that is added to the data.

13. A storage control apparatus according to claim 2, wherein:

the second data is data to which an error detecting code of the second kind is not added, and

in the case in which the data that is included in the first data is mis-corrected by using the error detecting code of the first kind, the mis-correction of the data is detected by using the error detecting code of the second kind that is added to the data.

14. A storage control apparatus according to claim 2, wherein:

the controller, the first communication interface, the second communication interface, the first memory area, and the second memory area are multiplexed,

in the (A), the controller judges whether or not data in the first memory module group that is provided with the error chip can be corrected based on the error detecting code of the first kind, and the controller executes the following steps in the case in which the result of the judgment is negative;

(a1) disabling the first memory module group that is provided with the error chip; and

(a2) in the case in which there is the user data that has not been stored into the physical storage device in the first memory module group that is provided with the error chip, copying user data that is equivalent to the user data from a first memory module group in a first memory area that is not provided with the error chip to a first memory module group that is not disabled in the first memory area that is provided with the error chip.

15. A storage control method comprising the steps of:

in the case of writing the first data to a first memory area, adding an error detecting code of the first kind to a first data element that is an element of the first data and writing the first data to the first memory area, wherein the first memory area is provided with at least one first memory module group, each of the first memory module group is provided with at least one first memory module, and each of the first memory module is provided with a plurality of memory chip;

in the case of writing the second data to the second memory area, adding an error detecting code of the first kind to a second data element that is an element of the second data and then writes the second data to the second memory area, wherein the second memory area is provided with at least one second memory module group, each of the second memory module group is provided with at least one second memory module, and each of the second memory module is provided with a plurality of memory chip;

in the case in which an error chip that is a memory chip that is provided with an error is a memory chip in the first memory module, not managing a first memory module group that is provided with the error chip as a memory module group that cannot be used even if there is a possibility that an error of the first data element is mis-corrected based on the error detecting code of the first kind; and

in the case in which an error chip that is a memory chip that is provided with an error is a memory chip in the second memory module, managing a second memory module group that is provided with the error chip as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind.