Creating A Thread Of Execution In A Computer Processor

• US 20120144396A1
• Filed: 12/02/2010
• Published: 06/07/2012
• Est. Priority Date: 12/02/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: GHEITH, AHMED, BOHRER, PATRICK J., PETERSON, JAMES L.
• Granted Patent: US 8,561,070 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

Creating a thread of execution in a computer processor, including copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state, and changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.

Claims

1. A method of creating a thread of execution in a computer processor, the method comprising:

copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state; and

changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.

2. The method of claim 1 further comprising:

calling, by the child hardware thread, an operating system function; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

3. The method of claim 1 further comprising:

receiving, by the computer processor, an asynchronous interrupt of the child hardware thread thereby invoking an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

4. The method of claim 1 further comprising:

causing, by the child hardware thread, an execution exception thereby invoking an interrupt handler of the operating system; and

creating, by the operating system , a canonical operating system thread descriptor for the child hardware thread.

5. The method of claim 1 wherein the hardware processor opcode further comprises an operand specifying a maximum number of child hardware threads to change from the wait state to the ephemeral run state, and the method further comprises:

returning, by the hardware processor opcode to the user-level process, a number of child hardware threads changed from the wait state to the ephemeral run state.

6. The method of claim 1 further comprising:

setting, by the hardware processor opcode for the parent hardware thread, a flag indicating whether any child hardware threads were changed from the wait state to the ephemeral run state.

7. The method of claim 1 further comprising:

setting, by the hardware processor opcode for the parent hardware thread, a flag identifying the parent hardware thread as a parent.

8. The method of claim 1 wherein changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state further comprises setting, by the hardware processor opcode for the child hardware thread, a flag identifying the child hardware thread as a child.

9. The method of claim 1 wherein changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state further comprises assigning, by the hardware processor opcode, a unique thread identifier to the child hardware thread including storing an integer in a register of the child hardware thread.

10. The method of claim 1 further comprising:

returning, by a hardware processor opcode executed in the child hardware thread, the child hardware thread to the wait state.

11. An apparatus for creating a thread of execution in a computer processor, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of:

copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state; and

changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.

12. The apparatus of claim 11 further comprising computer program instructions capable of:

calling, by the child hardware thread, an operating system function; and

creating, by the operating system , a canonical operating system thread descriptor for the child hardware thread.

13. The apparatus of claim 11 further comprising computer program instructions capable of:

receiving, by the computer processor, an asynchronous interrupt of the child hardware thread thereby invoking an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

14. The apparatus of claim 11 further comprising computer program instructions capable of:

causing, by the child hardware thread, an execution exception thereby invoking an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

15. The apparatus of claim 11 wherein the hardware processor opcode further comprises an operand specifying a maximum number of child hardware threads to change from the wait state to the ephemeral run state, and the apparatus further comprises computer program instructions capable of returning, by the hardware processor opcode to the user-level process, a number of child hardware threads changed from the wait state to the ephemeral run state.

16. The apparatus of claim 11 further comprising computer program instructions capable of setting, by the hardware processor opcode for the parent hardware thread, a flag indicating whether any child hardware threads were changed from the wait state to the ephemeral run state.

17. The apparatus of claim 11 further comprising computer program instructions capable of setting, by the hardware processor opcode for the parent hardware thread, a flag identifying the parent hardware thread as a parent.

18. A computer program product for creating a thread of execution in a computer processor, the computer program product disposed upon a computer readable storage medium, the computer program product comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of:

copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state; and

changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.

19. The computer program product of claim 18 further comprising computer program instructions causing the computer to carry out the steps of:

calling, by the child hardware thread, an operating system function; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

20. The computer program product of claim 18 further comprising computer program instructions causing the computer to carry out the steps of:

receiving, by the computer processor, an asynchronous interrupt of the child hardware thread thereby invoking an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

21. The computer program product of claim 18 further comprising computer program instructions causing the computer to carry out the steps of:

causing, by the child hardware thread, an execution exception thereby invoking an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

22. The computer program product of claim 18 wherein the hardware processor opcode further comprises an operand specifying a maximum number of child hardware threads to change from the wait state to the ephemeral run state, and the apparatus further comprises computer program instructions causing the computer to carry out the steps of returning, by the hardware processor opcode to the user-level process, a number of child hardware threads changed from the wait state to the ephemeral run state.

23. The computer program product of claim 18 further comprising computer program instructions causing the computer to carry out the steps of setting, by the hardware processor opcode for the parent hardware thread, a flag indicating whether any child hardware threads were changed from the wait state to the ephemeral run state.

24. The computer program product of claim 18 further comprising computer program instructions causing the computer to carry out the steps of setting, by the hardware processor opcode for the parent hardware thread, a flag identifying the parent hardware thread as a parent.