THIN FILM TRANSISTOR ARRAY PANEL

• US 20120146029A1
• Filed: 07/18/2011
• Published: 06/14/2012
• Est. Priority Date: 12/08/2010
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Woo Geun, YOON, Kap Soo, KIM, Ki-Won, CHOI, Young Joo, JIN, Sang Wan, SONG, Jae Won, Xun, Zhu
• Application Number:
  US13/185,105
• Publication Number:
  US 20120146029A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A thin film transistor array panel includes an insulating substrate, a gate line disposed on the insulating substrate having a gate electrode, a first gate insulating layer disposed on the gate line and made of silicon nitride, a second gate insulating layer disposed on the first gate insulating layer and made of silicon oxide, an oxide semiconductor disposed on the second gate insulating layer, a data line disposed on the oxide semiconductor and having a source electrode, a drain electrode disposed on the oxide semiconductor and facing the source electrode, and a pixel electrode that is connected to the drain electrode. A thickness of the second gate insulating layer may range from 200 Å to less than 500 Å.

Claims

1. A thin film transistor array panel, comprising:

a substrate;

a gate line disposed on the substrate and comprising a gate electrode;

a first gate insulating layer disposed on the gate line and comprising silicon nitride;

a second gate insulating layer disposed on the first gate insulating layer and comprising silicon oxide;

an oxide semiconductor disposed on the second gate insulating layer;

a data line disposed on the oxide semiconductor and comprising a source electrode;

a drain electrode disposed on the oxide semiconductor and facing the source electrode; and

a pixel electrode that is connected to the drain electrode,

wherein a thickness of the second gate insulating layer is greater than or equal to 200 Å and

less than 500 Å

.

2. The thin film transistor array panel of claim 1, wherein a thickness of the second gate insulating layer is 300 Å

.

3. The thin film transistor array panel of claim 2, wherein a thickness of the first gate insulating layer ranges from 2000 Å

to 5000 Å

.

4. The thin film transistor array panel of claim 3, wherein planar shapes and boundaries of the second gate insulating layer and the oxide semiconductor are the same as each other.

5. The thin film transistor array panel of claim 4, further comprising a channel passivation layer disposed on an exposed portion of the oxide semiconductor between the source electrode and the drain electrode.

6. The thin film transistor array panel of claim 5, further comprising a passivation layer disposed on the channel passivation layer.

7. The thin film transistor array panel of claim 6, wherein the channel passivation layer comprises silicon oxide, and the passivation layer comprises silicon nitride.

8. The thin film transistor array panel of claim 3, wherein the second gate insulating layer is disposed on an entire surface of the first gate insulating layer.

9. The thin film transistor array panel of claim 8, further comprising a first passivation layer disposed on the source electrode, the drain electrode, and an exposed oxide portion of the oxide semiconductor between the source electrode and drain electrode

10. The thin film transistor array panel of claim 9, further comprising a second passivation layer disposed on the first passivation layer.

11. The thin film transistor array panel of claim 10, wherein the first passivation layer comprises silicon oxide, and the second passivation layer comprises silicon nitride.

12. The thin film transistor array panel of claim 1, wherein the oxide semiconductor comprises at least one of an oxide of zinc, an oxide of gallium, an oxide of tin, an oxide of indium, zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO₄), indium zinc oxide (InZnO), or zinc tin oxide (ZnSnO), and mixtures thereof.