SEMICONDUCTOR DEVICE

• US 20120146154A1
• Filed: 02/17/2012
• Published: 06/14/2012
• Est. Priority Date: 10/23/2009
• Status: Active Grant

• Current Assignee: Pannova Semic, LLC (Vector Capital Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: KUTSUNAI, TOSHIE, AKAMATSU, SUSUMU, ITOU, SATORU, FUJIMOTO, HIROMASA
• Granted Patent: US 8,604,554 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.

Claims

1. A semiconductor device comprising:

a first MIS transistor; and

a second MIS transistor,

wherein

the first MIS transistor includes

a first gate insulating film formed on a first active region in a semiconductor substrate,

a first gate electrode formed on the first gate insulating film,

a first silicide layer formed on the first gate electrode,

first sidewalls each including a first inner sidewall formed on a side surface of the first gate electrode and having an L-shaped cross-section, and

first source/drain regions of a first conductivity type formed in the first active region laterally outside the first sidewalls,

the second MIS transistor includes

a second gate insulating film formed on a second active region in the semiconductor substrate,

a second gate electrode formed on the second gate insulating film,

a second silicide layer formed on the second gate electrode,

second sidewalls each including a second inner sidewall formed on a side surface of the second gate electrode and having an L-shaped cross-section, and

second source/drain regions of a second conductivity type formed in the second active region laterally outside the second sidewalls,

the first source/drain regions include a silicon compound layer which is formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region, and

a width of the first inner sidewall is smaller than a width of the second inner sidewall.

2. The semiconductor device of claim 1, wherein

a space between the first gate electrode and the silicon compound layer is smaller than the width of the second inner sidewall.

3. The semiconductor device of claim 1, wherein

a height of an upper surface of the first silicide layer is lower than a height of an upper surface of the second silicide layer.

4. The semiconductor device of claim 1, further comprising:

first offset spacers each formed between the first gate electrode and a corresponding one of the first inner sidewalls and having an I-shaped cross-section; and

second offset spacers each formed between the second gate electrode and a corresponding one of the second inner sidewalls and having an I-shaped cross-section.

5. The semiconductor device of claim 1, wherein

a thickness of the first inner sidewall is substantially the same as a thickness of the second inner sidewall.

6. The semiconductor device of claim 1, wherein

a thickness of the first inner sidewall is smaller than a thickness of the second inner sidewall.

7. The semiconductor device of claim 1, wherein

the first sidewalls each further include a first middle sidewall which is formed on a corresponding one of the first inner sidewalls and has an L-shaped cross-section,

the second sidewalls each further include a second middle sidewall which is formed on a corresponding one of the second inner sidewalls and has an L-shaped cross-section, and

a lower tip of the first middle sidewall is located further away from the first gate electrode than a lower tip of the first inner sidewall.

8. The semiconductor device of claim 1, further comprising:

a first stress insulating film which is formed on the first active region to cover the first gate electrode and the first sidewalls, and causes a stress in the same direction as that of the first stress, in the gate length direction of the channel region in the first active region.

9. The semiconductor device of claim 1, wherein

the first MIS transistor is a p-type MIS transistor, and

the first stress is a compressive stress.

10. The semiconductor device of claim 1, further comprising:

a second stress insulating film which is formed on the second active region to cover the second gate electrode and the second sidewalls and causes a second stress in a direction opposite to that of the first stress, in a gate length direction of a channel region in the second active region.

11. The semiconductor device of claim 10, wherein

the second MIS transistor is an n-type MIS transistor, and

the second stress is a tensile stress.

12. The semiconductor device of claim 1, further comprising:

a third MIS transistor including a third gate insulating film formed on a third active region in the semiconductor substrate, a third gate electrode formed on the third gate insulating film, third sidewalls formed on side surfaces of the third gate electrode, and third source/drain regions of the first conductivity type formed in the third active region laterally outside the third sidewalls,

wherein

the third sidewalls include third inner sidewalls formed on the side surfaces of the third gate electrode and having an L-shaped cross-section, third middle sidewalls formed on the third inner sidewalls and having an L-shaped cross-section, and third outer sidewalls formed on the third middle sidewalls,

the first sidewall and the second sidewall do not have an outer sidewall,

a silicon compound layer is not formed in the third source/drain regions, and

a width of the third inner sidewall is larger than the width of the first inner sidewall.

13. The semiconductor device of claim 12, further comprising:

a protective insulating film formed on the third gate electrode,

wherein

a silicide layer is not formed on the third gate electrode.

14. The semiconductor device of claim 1, wherein

a height of an upper end of the first inner sidewall is lower than a height of an upper end of the second inner sidewall.

15. The semiconductor device of claim 1, wherein

a height of an upper surface of the first gate electrode is lower than a height of an upper surface of the second gate electrode.