Thermal Conduction Paths for Semiconductor Structures

• US 20120146193A1
• Filed: 12/05/2011
• Published: 06/14/2012
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: IO Semiconductor, Inc
• Inventors: Stuber, Michael A., Brindle, Chris, Molin, Stuart B.
• Granted Patent: US 8,466,054 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.

Claims

1. A layer transferred semiconductor structure comprising:

a semiconductor wafer;

a handle wafer bonded to a top side of the semiconductor wafer;

an active device layer within the semiconductor wafer;

a substrate layer within the handle wafer; and

thermal conductivity material forming at least part of a thermal path from the active device layer to the substrate layer.

2. The layer transferred semiconductor structure of claim 1, further comprising:

a back side external thermal contact below the active device layer; and

second thermal conductivity material forming a second thermal path from the active device layer to the back side external thermal contact.

3. The layer transferred semiconductor structure of claim 2, wherein:

the second thermal path extends through the active device layer from the substrate layer to the back side external thermal contact; and

the first thermal path and the second thermal path are configured to act in combination with the substrate layer to form a thermally conductive path from the active device layer to the back side external thermal contact.

4. The layer transferred semiconductor structure of claim 1, wherein:

the thermal conductivity material comprises a mesh of solid metal and arrays of vias fabricated as stacks of material added at each step in an overall fabrication process for circuitry that surrounds the thermal conductivity material.

5. The layer transferred semiconductor structure of claim 1, wherein:

the thermal conductivity material comprises a single core of material formed using through semiconductor via processes.

6. The layer transferred semiconductor structure of claim 1, further comprising:

an interconnect layer within the semiconductor wafer above the active device layer;

a first region of the interconnect layer having a plurality of layers of conductive traces; and

a second region of the interconnect layer having fewer layers of conductive traces than the first region has;

and wherein the thermal conductivity material overlays the layers of conductive traces in the second region.

7. The layer transferred semiconductor structure of claim 1, further comprising:

a back side external thermal contact below the active device layer;

and wherein the thermal conductivity material extends through the active device layer from the substrate layer to the back side external thermal contact.

8. The layer transferred semiconductor structure of claim 1, wherein:

the thermal conductivity material is within in a trench formed up through the active device layer and at least partway to the substrate layer.

9. The layer transferred semiconductor structure of claim 8, wherein:

the thermal conductivity material also covers a substantial portion of a back side of the semiconductor wafer.

10. The layer transferred semiconductor structure of claim 1, further comprising:

a back side external thermal contact below the active device layer; and

an interconnect layer within the semiconductor wafer below the active device layer, the interconnect layer having at least one second thermal path from the active device layer to the back side external thermal contact.

11. A layer transferred semiconductor structure comprising:

a semiconductor wafer;

a handle wafer bonded to a top side of the semiconductor wafer;

an active device layer within the semiconductor wafer;

a back side external thermal contact below the active device layer; and

thermal conductivity material forming a thermal path from the active device layer to the back side external thermal contact.

12. The layer transferred semiconductor structure of claim 11, further comprising:

a substrate layer within the handle wafer;

and wherein;

the thermal conductivity material extends through the active device layer from the back side external thermal contact at least partway to the substrate layer.

13. The layer transferred semiconductor structure of claim 11, further comprising:

an interconnect layer within the semiconductor wafer below the active device layer;

and wherein the thermal path extends through the interconnect layer between the active device layer and the back side external thermal contact.

14. A method comprising:

forming an active device layer in a semiconductor wafer;

bonding a handle wafer to a top side of the semiconductor wafer; and

forming a thermal path in the semiconductor wafer, the thermal path being in contact with the active device layer.

15. The method of claim 14, further comprising:

forming the thermal path at least partway to a substrate layer of the handle wafer.

16. The method of claim 15, further comprising:

forming a back side external thermal contact on the semiconductor wafer; and

forming a second thermal path from the back side external thermal contact at least partway to the substrate layer of the handle wafer.

17. The method of claim 15, further comprising:

forming a back side external thermal contact on the semiconductor wafer; and

forming the thermal path in contact with the back side external thermal contact.

18. The method of claim 14, further comprising:

forming a back side external thermal contact on the semiconductor wafer; and

forming the thermal path to the back side external thermal contact.

19. The method of claim 14, further comprising:

forming the thermal path before the bonding of the handle wafer to the semiconductor wafer.

20. The method of claim 14, further comprising:

forming the thermal path after the bonding of the handle wafer to the semiconductor wafer.