PACKAGING SUBSTRATE HAVING THROUGH-HOLED INTERPOSER EMBEDDED THEREIN AND FABRICATION METHOD THEREOF

• US 20120146209A1
• Filed: 03/29/2011
• Published: 06/14/2012
• Est. Priority Date: 12/14/2010
• Status: Active Grant

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Unimicron Technology Corporation
• Inventors: Hu, Yu-Shan, Hu, Dyi-Chung, Tseng, Tzyy-Jang
• Granted Patent: US 8,269,337 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/1412 Layout
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/16267 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.

Claims

1. A packaging substrate having a through-holed interposer embedded therein, comprising:

a molding layer having a first surface and an opposite second surface;

the through-holed interposer embedded in the molding layer and having a first side and an opposite second side and a plurality of conductive through holes penetrating the first side and the second side, wherein each of the conductive through holes has a first end surface on the first side and a second end surface on the second side, and the second side of the through-holed interposer and the second end surfaces of the conductive through holes are flush with the second surface of the molding layer;

a redistribution-layer structure embedded in the molding layer and disposed on the first side of the through-holed interposer and the first end surfaces of the conductive through holes and electrically connected to the first end surfaces of the conductive through holes, wherein an outermost layer of the redistribution-layer structure has a plurality of electrode pads exposed from the first surface of the molding layer; and

a built-up structure disposed on the second surface of the molding layer, the second side of the through-holed interposer and the second end surfaces of the conductive through holes, wherein the built-up structure has a plurality of conductive vias, a portion of the conductive vias being electrically connected to the second end surfaces of the conductive through holes.

2. The substrate of claim 1, wherein the first surface of the molding layer has a plurality of first openings through which the electrode pads of the redistribution-layer structure are exposed for electrically connecting to a flip-chip semiconductor chip.

3. The substrate of claim 1, wherein the through-holed interposer is made of glass, ceramic, single crystal silicon or polysilicon.

4. The substrate of claim 3, wherein, if the through-holed interposer is made of single crystal silicon or polysilicon, each of the conductive through holes has an insulating layer formed on the side wall thereof.

5. The substrate of claim 1, wherein the through-holed interposer has a thickness between 75 μ

m and 150 μ

m.

6. The substrate of claim 1, wherein the built-up structure comprises at least a dielectric layer and a wiring layer formed on the dielectric layer, and the conductive vias are formed in the dielectric layer for electrically connecting the wiring layer and the second end surfaces of the conductive through holes.

7. The substrate of claim 6, further comprising an insulating protection layer formed on the built-up structure and having a plurality of second openings through which portions of the wiring layer are exposed to serve as conductive pads.

8. The substrate of claim 1, further comprising an antenna structure disposed on the first surface of the molding layer.

9. The substrate of claim 1, further comprising a first electronic component embedded in the molding layer and electrically connected to the built-up structure.

10. The substrate of claim 1, further comprising a second electronic component embedded in the molding layer and having a plurality of conductive pads exposed from the molding layer.

11. The substrate of claim 1, further comprising a heat sink disposed on the first surface of the molding layer and having an open region for exposing the electrode pads of the redistribution-layer structure and for receiving an electronic component.

12. A fabrication method of a packaging substrate having a through-holed interposer embedded therein, comprising the steps of:

providing a through-holed interposer having a redistribution-layer structure disposed thereon, wherein the through-holed interposer has a first side and an opposite second side and a plurality of conductive through holes penetrating the first side and the second side, each of the conductive through holes has a first end surface on the first side and a second end surface on the second side, the redistribution-layer structure is formed on the first side of the through-holed interposer and the first end surfaces of the conductive through holes and electrically connected to the first end surfaces of the conductive through holes, the second end surfaces of the conductive through holes are flush with the second side of the through-holed interposer so as to allow the second side and the second end surfaces of the conductive through holes to be attached to a carrier board, and an outermost layer of the redistribution-layer structure has a plurality of electrode pads;

forming a molding layer on the carrier board and the redistribution-layer structure so as to embed the through-holed interposer in the molding layer, wherein the molding layer has an exposed first surface and a second surface attached to the carrier board;

forming a metal layer on the first surface of the molding layer;

removing the carrier board to expose the second surface of the molding layer, the second side of the through-holed interposer and the second end surfaces of the conductive through holes;

forming a built-up structure on the second surface of the molding layer, the second side of the through-holed interposer, and the second end surfaces of the conductive through holes, wherein the built-up structure comprises a plurality of conductive vias, wherein a portion of the conductive vias are electrically connected to the second end surfaces of the conductive through holes;

removing the metal layer to expose the first surface of the molding layer; and

forming a plurality of first openings on the first surface of the molding layer for exposing the electrode pads, respectively.

13. The method of claim 12, wherein the through-holed interposer is made of single crystal silicon or polysilicon, the fabrication process of the through-holed interposer and the redistribution-layer structure comprising the steps of:

providing a substrate having a plurality of recesses;

forming an insulating layer on the substrate and a side wall of each of the recesses, a side of the substrate having the insulating layer being defined as the first side;

filling in the recesses with a metal material to form the conductive through holes, allowing the first end surfaces of the conductive through holes to be exposed from the first side and flush with the first side;

forming the redistribution-layer structure on the first side and the first end surfaces of the conductive through holes, wherein the redistribution-layer structure is electrically connected to the first end surfaces of the conductive through holes and the outermost layer of the redistribution-layer structure is formed with a plurality of electrode pads; and

removing a portion of the substrate below the recesses to form the second side of the through-holed interposer, so as for the second end surfaces of the conductive through holes to be exposed from the second side.

14. The method of claim 12, wherein the through-holed interposer is made of glass or ceramic, and the fabrication process of the through-holed interposer and the redistribution-layer structure comprises the steps of:

providing a substrate having one surface defined as the first side and a plurality of recesses formed on the first side;

filling in the recesses with a metal material so as to form the conductive through holes, the first end surfaces of the conductive through holes being exposed from the first side and flush with the first side;

forming the redistribution-layer structure on the first side and the first end surfaces of the conductive through holes, wherein the redistribution-layer structure is electrically connected to the first end surfaces of the conductive through holes and the outermost layer of the redistribution-layer structure is formed with a plurality of electrode pads; and

removing a portion of the substrate below the recesses to form the second side of the through-holed interposer, so as for the second end surfaces of the conductive through holes to be exposed from the second side.

15. The method of claim 12, wherein the through-holed interposer has a thickness between 75 μ

m and 150 μ

m.

16. The method of claim 12, wherein the built-up structure further comprises at least a dielectric layer and a wiring layer formed on the dielectric layer, and the conductive vias are disposed in the dielectric layer for electrically connecting the wiring layer and the second end surfaces of the conductive through holes.

17. The method of claim 16, further comprising the step of forming an insulating protection layer on the built-up structure and forming in the insulating protection layer a plurality of second openings through which portions of the wiring layer are exposed to serve as conductive pads.

18. The method of claim 12, further comprising the step of forming an antenna structure on the first surface of the molding layer.

19. The method of claim 12, further comprising the step of attaching a first electronic component on the carrier board so as to embed the first electronic component in the molding layer and electrically connect the first electronic component to the built-up structure.

20. The method of claim 19, wherein the first electronic component is an active component, a passive component or an integrated passive component.

21. The method of claim 12, further comprising the step of attaching on the carrier board a second electronic component having a plurality of conductive pads in a manner that the second electronic component is embedded in the molding layer and the conductive pads of the second electronic component are exposed from the molding layer.

22. The method of claim 21, wherein the second electronic component is an active component, a passive component or an integrated passive component.

23. The method of claim 12, further comprising the step of disposing a heat sink on the first surface of the molding layer, wherein the heat sink has an open region for exposing the electrode pads of the redistribution-layer and for receiving an electronic component.