LED CONTROLLER ASIC AND PWM MODULE THEREOF

• US 20120146535A1
• Filed: 12/09/2010
• Published: 06/14/2012
• Est. Priority Date: 12/09/2010
• Status: Abandoned Application

• Current Assignee: Goyatek, Inc. (Prolific Technology Inc.)
• Original Assignee: Goyatek, Inc. (Prolific Technology Inc.)
• Inventors: LEE, SHIH MING, YEN, HONG CHE, KAO, WEN LIN, CHEN, YUNG FU, LIN, TZAI DE
• Application Number:
  US12/963,871
• Publication Number:
  US 20120146535A1
• Time in Patent Office: Days
• US Class Current: 315/250
• CPC Class Codes: H05B 45/37 Converter circuits

Abstract

An LED controller application specific integrated circuit includes a host interface and a PWM module. The PWM module is configured to control a plurality of LED devices, and comprises a PWM data buffer, an arithmetic core and a plurality of PWM channels. The PWM data buffer is configured to store PWM turning-point data from the host. The arithmetic core is configured to generate PWM data according to the PWM turning-point data stored in the PWM data buffer. The plurality of PWM channels are configured to receive the PWM data, and each comprises a PWM controller and a PWM I/O interface. The PWM controller is configured to control the operation of the PWM channel. The PWM I/O interface is configured to connect to an LED device.

Claims

1. An LED controller ASIC, comprising:

a host interface, configured to connect to a host; and

a PWM module, configured to control a plurality of LED devices, comprising;

a PWM data buffer, configured to store PWM turning-point data from the host;

an arithmetic core, configured to generate PWM data according to the PWM turning-point data stored in the PWM data buffer; and

a plurality of PWM channels, configured to receive the PWM data, each comprising;

a PWM controller, configured to control the operation of the PWM channel; and

a PWM I/O interface, configured to connect to an LED device.

2. The LED controller ASIC of claim 1, wherein the host interface comprises an inter integrated circuit interface configured to receive serial data and clock input from the host.

3. The LED controller ASIC of claim 1, wherein each PWM channel is configured to issue an interrupt signal to the arithmetic core when the PWM channel is required to generate PWM data.

4. The LED controller ASIC of claim 3, wherein when a plurality of interrupt signals are received simultaneously, the arithmetic core is configured to retrieve corresponding PWM turning-point data from the PWM data buffer and generates PWM data in accordance with priority levels of the plurality of interrupt signals.

5. The LED controller ASIC of claim 1, wherein each PWM channel is operable in a normal mode in accordance with a first clock signal and a sleep mode in accordance with a second clock signal, and the clock rate of the first clock signal is higher than that of the second clock signal.

6. The LED controller ASIC of claim 5, wherein the mode of each PWM channel is determined by instructions issued by the host.

7. The LED controller ASIC of claim 6, wherein each PWM channel operated in the normal mode is configured to output PWM data and control the operation of the LED device connected to the PWM I/O interface of the PWM channel.

8. The LED controller ASIC of claim 7, wherein each PWM channel operated in the normal mode comprises the following states:

a normal idle state, in which the PWM channel is idle until receiving an instruction issued by the host;

a calculation state, in which the arithmetic core generates PWM data for the PWM channel;

a wait state, in which the PWM I/O interface of the PWM channel loads the PWM data to the LED device connected to the PWM I/O interface of the PWM channel;

a count state, in which the PWM channel maintains its PWM data after a predetermined time; and

a hold state, in which the PWM channel holds its PWM data until receiving an instruction issued by the host or after a predetermined time.

9. The LED controller ASIC of claim 6, wherein each PWM channel operated in the sleep mode is configured to resume its original state after a predetermined time.

10. The LED controller ASIC of claim 9, wherein each PWM channel operated in the sleep mode comprises the following states:

a sleep idle state, in which the PWM channel is idle for a predetermined time;

a load state, in which the PWM channel loads a counter value;

a sleep count state, in which the PWM channel counts until the counter value is reached; and

an update state, in which the PWM channel updates its state.

11. The LED controller ASIC of claim 1, wherein the PWM data buffer is implemented by registers or an SRAM.

12. The LED controller ASIC of claim 1, further comprising:

an I/O interface, configured to connect to I/O peripherals;

a reset circuit, configured to issue a reset interrupt when receiving a reset signal from the I/O interface and then issue a reset signal after the issue of the reset interrupt; and

wherein there is a predetermined time interval between the issuing of the reset interrupt and the issuing of the reset signal.

13. The LED controller ASIC of claim 12, wherein the reset signal is a combination of input signals.

14. The LED controller ASIC of claim 13, wherein the reset circuit comprises:

a reset scale module, configured to provide a frequency division signal of a clock signal;

a de-bounce module, configure to smooth the reset signal with the sampling rate determined by the frequency division signal; and

a control logic, configure to issue the reset interrupt and the reset signal.

15. The LED controller ASIC of claim 1, further comprising:

a clock correct circuit, configured to calibrate an internal clock signal based on an external clock signal.

16. The LED controller ASIC of claim 15, wherein the clock correct circuit comprises:

a counter, configured to count the pulse number of the clock signal with higher clock rate among the internal clock signal and the external clock signal within a pulse of the clock signal with lower clock rate among the internal clock signal and the external clock signal; and

wherein the clock correct circuit is configured to adjust the clock rate of the internal clock signal when the counted number is not within a predetermined range.

17. The LED controller ASIC of claim 1, being configured to control an LED indicator or a backlight device of a mobile phone.

18. A PWM module in an LED controller circuit for controlling a plurality of LED devices, comprising:

a PWM data buffer, configured to store PWM turning-point data from a host;

an arithmetic core, configured to generate PWM data according to the PWM turning-point data stored in the PWM data buffer; and

a plurality of PWM channels, configured to receive the PWM data, each comprising;

a PWM controller, configured to control the operation of the PWM channel; and

a PWM I/O interface, configured to connected to an LED device.

19. The PWM module of claim 18, wherein each PWM channel is configured to issue an interrupt signal to the arithmetic core when the PWM channel is required to generate PWM data.

20. The PWM module of claim 19, wherein when a plurality of interrupt signals are received simultaneously, the arithmetic core is configured to retrieve corresponding PWM turning-point data from the PWM data buffer and generates PWM data in accordance with priority levels of the plurality of interrupt signals.

21. The PWM module of claim 18, wherein each PWM channel is operable in a normal mode in accordance with a first clock signal and a sleep mode in accordance with a second clock signal, and the clock rate of the first clock signal is higher than that of the second clock signal.

22. The PWM module of claim 21, wherein the mode of each PWM channel is determined by instructions issued by the host.

23. The PWM module of claim 22, wherein each PWM channel operated in the normal mode is configured to output PWM data and control the operation of the LED device connected to the PWM I/O interface of the PWM channel.

24. The PWM module of claim 23, wherein each PWM channel operated in the normal mode comprises the following states:

a normal idle state, in which the PWM channel is idle until receiving an instruction issued by the host;

a calculation state, in which the arithmetic core generates PWM data for the PWM channel;

a wait state, in which the PWM I/O interface of the PWM channel loads the PWM signal to the LED device connected to the PWM I/O interface of the PWM channel;

a count state, in which the PWM channel maintains its PWM data after a predetermined time; and

a hold state, in which the PWM channel holds its PWM data until receiving an instruction issued by the host.

25. The PWM module of claim 22, wherein each PWM channel operated in the sleep mode is configured to resume its original state after a predetermined time.

26. The PWM module of claim 25, wherein each PWM channel operated in the sleep mode comprises the following states:

a sleep idle state, in which the PWM channel is idle for a predetermined time;

a load state, in which the PWM channel loads a counter value;

a sleep count state, in which the PWM channel counts until the counter value is reached; and

an update state, in which the PWM channel updates its state

27. The PWM module of claim 18, wherein the PWM data buffer is implemented by registers or an SRAM.

28. The PWM module of claim 18, being configured to control an LED indicator or a backlight device of a mobile phone.