DIFFERENTIAL CONTROLLED PHASE LOCKED LOOP CIRCUIT

• US 20120146692A1
• Filed: 09/23/2011
• Published: 06/14/2012
• Est. Priority Date: 12/08/2010
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: YUN, Seok Ju
• Granted Patent: US 8,508,265 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop

Abstract

Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.

Claims

1. A Phase Locked Loop (PLL) circuit comprising:

a Voltage Controlled Oscillator (VCO) outputting an oscillation signal in response to a difference between first and second control voltages,

wherein;

the PLL circuit comprises a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage, and

intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.

2. The PLL circuit of claim 1, wherein:

the first loop comprises a first phase frequency detector detecting phase and frequency differences between a reference signal and a division signal for the oscillation signal, and

the second loop comprises a second phase frequency detector detecting phase and frequency differences between an inverted reference signal and an inverted division signal.

3. The PLL circuit of claim 2, wherein:

the first loop further comprises a first charge pump controlling a first output current which corresponds to the first control voltage according to the detected result of the first phase frequency detector, and

the second loop further comprises a second charge pump controlling a second output current which corresponds to the second control voltage according to the detected result of the second phase frequency detector.

4. A Phase Locked Loop (PLL) circuit comprising:

a first phase frequency detector outputting a first differential control signal in response to a reference signal and a division signal for an oscillation signal;

a second phase frequency detector outputting a second differential control signal in response to an inverted reference signal and an inverted division signal;

a first charge pump outputting a first current which is controlled according to the first differential control signal;

a second charge pump outputting a second current which is controlled according to the second differential control signal;

a first loop filter outputting a first control voltage which corresponds to the first current;

a second loop filter outputting a second control voltage which corresponds to the second current; and

a Voltage Controlled Oscillator (VCO) outputting the oscillation signal in response to a difference between the first and second control voltages.

5. The PLL circuit of claim 4, wherein the first and second differential control signals have opposed phases.

6. The PLL circuit of claim 4, wherein the first and second currents have opposed phases.

7. The PLL circuit of claim 4, wherein the first and second control voltages have opposed phases.

8. The PLL circuit of claim 4, further comprising a delay circuit delaying the reference signal and the division signal by a half cycle to generate the inverted reference signal and the inverted division signal, respectively.

9. The PLL circuit of claim 4, further comprising:

a first switch selectively connecting the first charge pump and the first loop filter in response to a first switch control signal; and

a second switch selectively connecting the second charge pump and the second loop filter in response to a second switch control signal.

10. The PLL circuit of claim 4, further comprising a common mode feedback circuit feeding back a Direct Current (DC) voltage to the first and second charge pumps, wherein the DC voltage is outputted in response to change of the first and second currents.

11. A Phase Locked Loop (PLL) circuit comprising:

a first phase frequency detector outputting a first differential control signal in response to a reference signal and a division signal for an oscillation signal;

a second phase frequency detector outputting a second differential control signal in response to an inverted reference signal and an inverted division signal;

first to third charge pumps outputting first to third currents which are controlled according to the first differential control signal, respectively;

a second charge pump outputting a fourth current which is controlled according to the second differential control signal;

a first loop filter outputting a first control voltage which corresponds to sum of the first and second currents;

a second loop filter outputting a second control voltage which corresponds to sum of the third and fourth currents; and

a Voltage Controlled Oscillator (VCO) outputting the oscillation signal in response to a difference between the first and second control voltages.

12. The PLL circuit of claim 11, wherein the second differential control signal has a phase which has been further delayed by a half cycle of the reference signal than the first differential control signal.

13. The PLL circuit of claim 11, wherein the fourth current has a phase which has been further delayed by a half cycle of the reference signal than the first to third currents.

14. The PLL circuit of claim 11, wherein:

the first control voltage is changed at every cycle of the reference signal, and

the second control voltage is changed at every half cycle of the reference signal.

15. The PLL circuit of claim 11, further comprising a common mode feedback circuit maintaining constant sum of the first to fourth currents.

16. The PLL circuit of claim 11, further comprising a switch circuit selectively connecting the first and second charge pumps to the first loop filter, and selectively connecting the third and fourth charge pumps to the second loop filter, according to an external switch control signal.