CIRCUIT AND METHOD FOR SENSING A CAPACITANCE

• US 20120146726A1
• Filed: 12/09/2011
• Published: 06/14/2012
• Est. Priority Date: 12/10/2010
• Status: Active Grant

• Current Assignee: Elan Microelectronics Corporation
• Original Assignee: Elan Microelectronics Corporation
• Inventors: HUANG, Chun-Chung, Chiu, Te-Sheng, Hsu, Shih-Yuan, Lee, I-Shu
• Granted Patent: US 9,075,486 B2
• Time in Patent Office: Days
• US Class Current: 330/257
• CPC Class Codes: G01D 5/24 by varying capacitance
• CPC Class Codes: G01R 1/30 Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06F 3/041662 using alternate mutual and self-capacitive scanning
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H03F 2200/474 A current mirror being used as sensor
• CPC Class Codes: H03F 3/04 with semiconductor devices only

Abstract

A transconductance amplifier mirror circuit is connected to an electrode for sensing the capacitance of the electrode with reference to ground, or the capacitance between the electrode and another electrode. A voltage level change is produced on the electrode connected to the transconductance amplifier mirror circuit to cause the transconductance amplifier mirror circuit to supply charges to or drain charges from a charge calculation circuit. The charge amount variation is converted to a signal for calculating the sensed capacitance.

Claims

1. A circuit for sensing a capacitance between a first electrode and a second electrode, comprising:

a switching circuit connected to the first electrode, controlled to change a voltage level of the first electrode;

a transconductance amplifier mirror circuit including a first output port and a second output port, the first output port being controlled to connect to the second electrode, the transconductance amplifier mirror circuit being operative to maintain a voltage level of the first output port at a reference voltage and thereby cause a charge amount variation at the second output port responsive to a voltage variation at the first output port; and

a charge calculation circuit connected to the second output port of the transconductance amplifier mirror circuit, operative to generate a sensed signal responsive to the charge amount variation.

2. The circuit of claim 1, wherein the switching circuit comprises a switch controlled to switch the voltage level of the first electrode to a higher voltage level higher than the reference voltage, or to a lower voltage level lower than the reference voltage.

3. The circuit of claim 2, wherein the transconductance amplifier mirror circuit comprises:

a first transconductance amplifier connected to the first output port of the transconductance amplifier mirror circuit, operative to supply a first amount of charges to or drain a second amount of charges from the first output port responsive to a difference between a voltage level of the second electrode and the reference voltage; and

a second transconductance amplifier connected to the first transconductance amplifier and the second output port of the transconductance amplifier mirror circuit, operative to supply a third amount of charges to or drain a fourth amount of charges from the second output port, wherein the third amount of charges is proportional to the first amount of charges, and the fourth amount of charges is proportional to the second amount of charges.

4. The circuit of claim 3, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the third amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the reference voltage or the lower voltage level.

5. The circuit of claim 3, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the fourth amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the reference voltage or the higher voltage level.

6. The circuit of claim 2, wherein the transconductance amplifier mirror circuit comprises:

a comparator connected to the first output port of the transconductance amplifier mirror circuit, comparing a voltage level of the second electrode with the reference voltage to generate an error signal;

a first PMOS transistor connected to the comparator and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a first amount of charges to the first output port;

a second PMOS transistor connected to the comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a second amount of charges to the second output port, wherein the second amount of charges is proportional to the first amount of charges; and

a control unit connected to the first output port of the transconductance amplifier mirror circuit, operative to maintain the first output port at the reference voltage before the switching circuit changes the voltage level of the first electrode.

7. The circuit of claim 6, wherein the comparator comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

8. The circuit of claim 6, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the second amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the reference voltage or the lower voltage level.

9. The circuit of claim 2, wherein the transconductance amplifier mirror circuit comprises:

a comparator connected to the first output port of the transconductance amplifier mirror circuit, comparing a voltage level of the second electrode with the reference voltage to generate an error signal;

a first NMOS transistor connected to the comparator and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a first amount of charges from the first output port;

a second NMOS transistor connected to the comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a second amount of charges from the second output port, wherein the second amount of charges is proportional to the first amount of charges; and

a control unit connected to the first output port of the transconductance amplifier mirror circuit, operative to maintain the first output port at the reference voltage before the switching circuit changes the voltage level of the first electrode.

10. The circuit of claim 9, wherein the comparator comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

11. The circuit of claim 9, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the second amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the reference voltage or the higher voltage level.

12. The circuit of claim 2, wherein the transconductance amplifier mirror circuit comprises:

a comparator connected to the first output port of the transconductance amplifier mirror circuit, comparing a voltage level of the second electrode with the reference voltage to generate an error signal;

a first switch connected to the comparator;

a first PMOS transistor connected to the first switch and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a first amount of charges to the first output port when the first switch is on;

a second PMOS transistor connected to the first switch and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a second amount of charges to the second output port when the first switch is on, wherein the second amount of charges is proportional to the first amount of charges;

a second switch connected to the comparator;

a first NMOS transistor connected to the second switch and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a third amount of charges from the first output port when the second switch is on;

a second NMOS transistor connected to the second switch and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a fourth amount of charges from the second output port when the second switch is on, wherein the fourth amount of charges is proportional to the third amount of charges; and

a control unit connected to the first output port of the transconductance amplifier mirror circuit, operative to maintain the first output port at the reference voltage before the switching circuit changes the voltage level of the first electrode.

13. The circuit of claim 12, wherein the comparator comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

14. The circuit of claim 12, wherein the charge calculation circuit comprises:

a third switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the first switch;

a fourth switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the second switch;

a first capacitor connected to the third switch, receiving the second amount of charges during the third switch is on;

a first initialization switch connected to the first capacitor, controlled to initialize a voltage level of the first capacitor to the lower voltage level;

a second capacitor connected to the fourth switch, sourcing the fourth amount of charges during the fourth switch is on;

a second initialization switch connected to the second capacitor, controlled to initialize a voltage level of the second capacitor to the higher voltage level; and

an adder connected to the first and second capacitors, summing up the variations of charges on the first and second capacitors to generate the sensed signal.

15. The circuit of claim 2, wherein the transconductance amplifier mirror circuit comprises:

a first switch and a second switch, both connected to the first output port of the transconductance amplifier mirror circuit;

a first comparator connected to the first switch, comparing a voltage level of the second electrode with the reference voltage to generate a first error signal when the first switch is on;

a second comparator connected to the second switch, comparing the voltage level of the second electrode with the reference voltage to generate a second error signal when the second switch is on;

a first PMOS transistor connected to the first switch and the first comparator, controlled by the first error signal to supply a first amount of charges to the first output port when the first switch is on;

a second PMOS transistor connected to the first comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the first error signal to supply a second amount of charges to the second output port when the first switch is on, wherein the second amount of charges is proportional to the first amount of charges;

a first NMOS transistor connected to the second switch and the second comparator, controlled by the second error signal to drain a third amount of charges from the first output port when the second switch is on;

a second NMOS transistor connected to the second comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the second error signal to drain a fourth amount of charges from the second output port when the second switch is on, wherein the fourth amount of charges is proportional to the third amount of charges; and

a control unit connected to the first output port of the transconductance amplifier mirror circuit, operative to maintain the first output port at the reference voltage before the switching circuit changes the voltage level of the first electrode.

16. The circuit of claim 15, wherein each of the first and second comparators comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

17. The circuit of claim 15, wherein the charge calculation circuit comprises:

a third switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the first switch;

a fourth switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the second switch;

a first capacitor connected to the third switch, receiving the second amount of charges during the third switch is on;

a first initialization switch connected to the first capacitor, controlled to initialize a voltage level of the first capacitor to the lower voltage level;

a second capacitor connected to the fourth switch, sourcing the fourth amount of charges during the fourth switch is on;

a second initialization switch connected to the second capacitor, controlled to initialize a voltage level of the second capacitor to the higher voltage level; and

an adder connected to the first and second capacitors, summing up the variations of charges on the first and second capacitors to generate the sensed signal.

18. A circuit for sensing a capacitance of an electrode with reference to ground, comprising:

a switching circuit connected to the electrode, controlled to change a voltage level of the electrode;

a transconductance amplifier mirror circuit including a first output port and a second output port, operative to maintain a voltage level of the first output port at a reference voltage and thereby cause a charge amount variation at the second output port responsive to a voltage variation at the first output port;

a sensing switch connected between the electrode and the first output port of the transconductance amplifier mirror circuit, controlled to connect the first output port to the electrode; and

a charge calculation circuit connected to the second output port of the transconductance amplifier mirror circuit, operative to generate a sensed signal responsive to the charge amount variation.

19. The circuit of claim 18, wherein the switching circuit comprises a switch controlled to switch the voltage level of the electrode to a lower voltage level lower than the reference voltage.

20. The circuit of claim 19, wherein the transconductance amplifier mirror circuit comprises:

a first transconductance amplifier connected to the first output port of the transconductance amplifier mirror circuit, operative to supply a first amount of charges to the first output port responsive to a difference between the voltage level of the electrode and the reference voltage; and

a second transconductance amplifier connected to the first transconductance amplifier and the second output port of the transconductance amplifier mirror circuit, operative to supply a second amount of charges to the second output port, wherein the second amount of charges is proportional to the first amount of charges.

21. The circuit of claim 20, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the second amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the lower voltage level.

22. The circuit of claim 19, wherein the transconductance amplifier mirror circuit comprises:

a comparator connected to the first output port of the transconductance amplifier mirror circuit, comparing the voltage level of the electrode with the reference voltage to generate an error signal;

a first PMOS transistor connected to the comparator and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a first amount of charges to the first output port; and

a second PMOS transistor connected to the comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a second amount of charges to the second output port, wherein the second amount of charges is proportional to the first amount of charges.

23. The circuit of claim 22, wherein the comparator comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

24. The circuit of claim 22, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the second amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the lower voltage level.

25. The circuit of claim 18, wherein the switching circuit comprises a switch controlled to switch the voltage level of the electrode to a higher voltage level higher than the reference voltage.

26. The circuit of claim 25, wherein the transconductance amplifier mirror circuit comprises:

a first transconductance amplifier connected to the first output port of the transconductance amplifier mirror circuit, operative to drain a first amount of charges from the first output port responsive to a difference between the voltage level of the electrode and the reference voltage; and

a second transconductance amplifier connected to the first transconductance amplifier and the second output port of the transconductance amplifier mirror circuit, operative to drain a second amount of charges from the second output port, wherein the second amount of charges is proportional to the first amount of charges.

27. The circuit of claim 26, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the second amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the higher voltage level.

28. The circuit of claim 25, wherein the transconductance amplifier mirror circuit comprises:

a comparator connected to the first output port of the transconductance amplifier mirror circuit, comparing the voltage level of the electrode with the reference voltage to generate an error signal;

a first NMOS transistor connected to the comparator and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a first amount of charges from the first output port; and

a second NMOS transistor connected to the comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a second amount of charges from the second output port, wherein the second amount of charges is proportional to the first amount of charges.

29. The circuit of claim 28, wherein the comparator comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

30. The circuit of claim 28, wherein the charge calculation circuit comprises:

a capacitor connected to the second output port of the transconductance amplifier mirror circuit, responsive to the second amount of charges to generate the sensed signal; and

an initialization switch connected to the capacitor, controlled to initialize a voltage level of the capacitor to the higher voltage level.

31. The circuit of claim 18, wherein the switching circuit comprises a switch controlled to switch the voltage level of the electrode to a higher voltage level higher than the reference voltage, or to a lower voltage level lower than the reference voltage.

32. The circuit of claim 31, wherein the transconductance amplifier mirror circuit comprises:

a first transconductance amplifier connected to the first output port of the transconductance amplifier mirror circuit, operative to supply a first amount of charges to or drain a second amount of charges from the first output port responsive to a difference between the voltage level of the electrode and the reference voltage; and

a second transconductance amplifier connected to the first transconductance amplifier and the second output port of the transconductance amplifier mirror circuit, operative to supply a third amount of charges to or drain a fourth amount of charges from the second output port, wherein the third amount of charges is proportional to the first amount of charges, and the fourth amount of charges is proportional to the second amount of charges.

33. The circuit of claim 31, wherein the transconductance amplifier mirror circuit comprises:

a comparator connected to the first output port of the transconductance amplifier mirror circuit, comparing the voltage level of the electrode with the reference voltage to generate an error signal;

a first switch connected to the comparator;

a first PMOS transistor connected to the first switch and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a first amount of charges to the first output port when the first switch is on;

a second PMOS transistor connected to the first switch and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to supply a second amount of charges to the second output port when the first switch is on, wherein the second amount of charges is proportional to the first amount of charges;

a second switch connected to the comparator;

a first NMOS transistor connected to the second switch and the first output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a third amount of charges from the first output port when the second switch is on; and

a second NMOS transistor connected to the second switch and the second output port of the transconductance amplifier mirror circuit, controlled by the error signal to drain a fourth amount of charges from the second output port when the second switch is on, wherein the fourth amount of charges is proportional to the third amount of charges.

34. The circuit of claim 33, wherein the comparator comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

35. The circuit of claim 33, wherein the charge calculation circuit comprises:

a third switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the first switch;

a fourth switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the second switch;

a first capacitor connected to the third switch, receiving the second amount of charges during the third switch is on;

a first initialization switch connected to the first capacitor, controlled to initialize a voltage level of the first capacitor to the lower voltage level;

a second capacitor connected to the fourth switch, sourcing the fourth amount of charges during the fourth switch is on;

a second initialization switch connected to the second capacitor, controlled to initialize a voltage level of the second capacitor to the higher voltage level; and

an adder connected to the first and second capacitors, summing up the variations of charges on the first and second capacitors to generate the sensed signal.

36. The circuit of claim 31, wherein the transconductance amplifier mirror circuit comprises:

a first switch and a second switch, both connected to the first output port of the transconductance amplifier mirror circuit;

a first comparator connected to the first switch, comparing the voltage level of the electrode with the reference voltage to generate a first error signal when the first switch is on;

a second comparator connected to the second switch, comparing the voltage level of the electrode with the reference voltage to generate a second error signal when the second switch is on;

a first PMOS transistor connected to the first switch and the first comparator, controlled by the first error signal to supply a first amount of charges to the first output port when the first switch is on;

a second PMOS transistor connected to the first comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the first error signal to supply a second amount of charges to the second output port when the first switch is on, wherein the second amount of charges is proportional to the first amount of charges;

a first NMOS transistor connected to the second switch and the second comparator, controlled by the second error signal to drain a third amount of charges from the first output port when the second switch is on; and

a second NMOS transistor connected to the second comparator and the second output port of the transconductance amplifier mirror circuit, controlled by the second error signal to drain a fourth amount of charges from the second output port when the second switch is on, wherein the fourth amount of charges is proportional to the third amount of charges.

37. The circuit of claim 36, wherein each of the first and second comparators comprises an operational amplifier, an operational transconductance amplifier, or an error amplifier.

38. The circuit of claim 36, wherein the charge calculation circuit comprises:

a third switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the first switch;

a fourth switch connected to the second output port of the transconductance amplifier mirror circuit, switched simultaneously with the second switch;

a first capacitor connected to the third switch, receiving the second amount of charges during the third switch is on;

a first initialization switch connected to the first capacitor, controlled to initialize a voltage level of the first capacitor to the lower voltage level;

a second capacitor connected to the fourth switch, sourcing the fourth amount of charges during the fourth switch is on;

a second initialization switch connected to the second capacitor, controlled to initialize a voltage level of the second capacitor to the higher voltage level; and

an adder connected to the first and second capacitors, summing up the variations of charges on the first and second capacitors to generate the sensed signal.

39. A method for sensing a capacitance between a first electrode and a second electrode, comprising the steps of:

A) changing a voltage level of the first electrode;

B) maintaining a voltage level of the second electrode at a reference voltage to cause a charge amount variation responsive to a voltage variation at the second electrode; and

C) generating a sensed signal responsive to the charge amount variation.

40. The method of claim 39, wherein the step B comprises the steps of:

supplying a first amount of charges to or draining a second amount of charges from the second electrode responsive to a difference between the voltage level of the second electrode and the reference voltage; and

supplying a third amount of charges or draining a fourth amount of charges, wherein the third amount of charges is proportional to the first amount of charges, and the fourth amount of charges is proportional to the second amount of charges.

41. The method of claim 40, wherein the step C comprises the step of generating the sensed signal responsive to the third amount of charges or the fourth amount of charges.

42. A method for sensing a capacitance of an electrode with reference to ground, comprising the steps of:

A) changing a voltage level of the electrode;

B) maintaining the voltage level of the electrode at a reference voltage to cause a charge amount variation responsive to a voltage variation at the electrode; and

C) generating a sensed signal responsive to the charge amount variation.

43. The method of claim 42, wherein the step B comprises the steps of:

supplying a first amount of charges to or draining a second amount of charges from the electrode responsive to a difference between the voltage level of the electrode and the reference voltage; and

supplying a third amount of charges or draining a fourth amount of charges, wherein the third amount of charges is proportional to the first amount of charges, and the fourth amount of charges is proportional to the second amount of charges.

44. The method of claim 43, wherein the step C comprises the step of generating the sensed signal responsive to the third amount of charges or the fourth amount of charges.