THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL LAYERS OF SELECT DEVICES

• US 20120147651A1
• Filed: 12/12/2011
• Published: 06/14/2012
• Est. Priority Date: 12/14/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Cernea, Raul-Adrian
• Granted Patent: US 9,030,859 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10N 70/043 by implantation
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Claims

1. A non-volatile storage system, comprising:

a monolithic three dimensional memory array of memory cells;

word lines connected to the memory cells;

a plurality of vertically oriented bit lines connected to the memory cells;

a plurality of global bit lines;

a first plurality of select devices that are connected to the global bit lines;

a second plurality of select devices that are connected to the vertically oriented bit lines and the first plurality of select devices, the first plurality of select devices are on a first level and the second plurality of select devices are on a second level that is above the first level; and

select lines connect to the first plurality of select devices and the second plurality of select devices.

2. The non-volatile storage system of claim 1, wherein:

each select device of the first plurality of select devices is on top of a corresponding select device of the second plurality of select devices.

3. The non-volatile storage system of claim 2, wherein:

each select device of the first plurality of select devices is connected to the corresponding select device of the second plurality of select devices.

4. The non-volatile storage system of claim 3, wherein:

each select device of the first plurality of select devices is in series with the corresponding select device of the second plurality of select devices.

5. The non-volatile storage system of claim 1, wherein:

each select device of the first plurality of select devices includes two gate interfaces;

each select device of the second plurality of select devices includes two gate interfaces; and

the select lines comprise a first plurality of select lines each connected to two gate interfaces of the first plurality of select devices and a second plurality of select lines each connected to two gate interfaces of the second plurality of select devices, the first plurality of select lines are on the first level and the second plurality of select lines are on the second level.

6. The non-volatile storage system of claim 5, wherein:

a particular vertically oriented bit line is put in communication with a particular global bit by turning on a first select device from the first plurality of select devices and a second select device from the second plurality of select devices such that the first select device is connected to the particular global bit and the second select device is connected to the particular vertically oriented bit line, first select device is connected to the second select device; and

turning on the first select device and the second select device includes selecting a first select line from the first plurality of select lines and a second select line from the second plurality of select lines, the first select line is on an opposite side of the first select device and the second select device as the second select line.

7. The non-volatile storage system of claim 1, wherein:

diagonal pairs of select lines are connected together, each diagonal pair includes one select line from the first plurality of select lines and one select line from the second plurality of select lines that is on an opposite side of a pair of connected in series select devices.

8. The non-volatile storage system of claim 1, wherein:

a particular vertically oriented bit line is put in communication with a particular global bit by selecting a first select line from the first plurality of select lines and a second select line from the second plurality of select lines such that the first select line is on an opposite side of a pair of connected in series select devices as the second select line.

9. The non-volatile storage system of claim 1, wherein:

the memory cells are grouped into blocks;

between blocks, select lines exist as single signal lines; and

underneath blocks, select lines split into multiple signal lines including a first line and a second line, the first line connects to select devices of the first plurality of select devices, the second line connects to select devices of the second plurality of select devices.

10. The non-volatile storage system of claim 1, further comprising:

row select line drivers, the memory cells are arranged in blocks, the memory array includes gaps between blocks, and each row select line driver includes multiple components that are distributed in different gaps between blocks and connect to the select lines in the gaps.

11. The non-volatile storage system of claim 1, further comprising:

a substrate, the monolithic three dimensional memory array of memory cells is positioned above and not in the substrate, the vertically oriented bit lines are positioned above and not in the substrate, the first plurality of select devices and the second plurality of select devices are vertically oriented select devices that are above and not in the substrate, groups of word lines are connected together.

12. The non-volatile storage system of claim 1, wherein:

a particular vertically oriented bit line is put in communication with a particular global bit by turning on a first select device from the first plurality of select devices and a second select device from the second plurality of select devices such that the first select device is connected to the particular global bit and the second select device is connected to the particular vertically oriented bit line, first select device is connected to the second select device;

turning on the first select device and the second select device includes selecting a first select line and a second select line, the first select line is on an opposite side of the first select device and the second select device as the second select line; and

the first select line is also connected to another select device adjacent the first select device, the second select line is also connected to another select device adjacent the second select device.

13. A method of operating a storage system comprising a monolithic three dimensional memory array of memory cells, vertically oriented bit lines and word lines are connected to the memory cells, the method comprising:

applying a selected word line voltage to a word line connected to a selected memory cell, a selected vertically oriented bit line is also connected to the selected memory cell;

applying a selected bit line voltage to selected global bit lines based on a data pattern, the global bit lines communicate with the vertically oriented bit lines via a first plurality of select devices that are connected to the global bit lines and a second plurality of select devices that are connected to the vertically oriented bit lines and the first plurality of select devices, the first plurality of select devices are on a first level and the second plurality of select devices are on a second level that is above the first level;

turning on a first select device from the first plurality of select devices and a second select device from the second plurality of select devices by applying a first selection signal to a first select line connected to the first select device and applying a second selection signal to a second select line connected to the second select device, the first select line is on an opposite side of a stack than the second select line in which the stack includes the first select device and the second select device connected together in series; and

performing a memory operation in the selected memory cell in response to the selected bit line voltage and the selected word line voltage.

14. The method of claim 13, wherein:

the first select line is also connected to another select device adjacent the first select device, the second select line is also connected to another select device adjacent the second select device.

15. The method of claim 13, wherein:

the applying the selected word line voltage to the selected word line comprises applying the selected word line voltage to a group of connected word lines.

16. The method of claim 13, further comprising:

before applying the selected word line voltage, applying an unselected word line voltage to unselected word lines; and

before applying the selected bit line voltage, applying an unselected bit line voltage to global bit lines.

17. The method of claim 16, further comprising:

after applying the unselected word line voltage, floating vertically oriented bit lines so that the vertically oriented bit lines drift toward the unselected word line voltage.

18. The method of claim 13, wherein:

the memory cells are arranged in blocks and the memory array includes gaps between blocks; and

the applying a first selection signal to a first select line includes driving the first select line from components in the gaps.

19. A non-volatile storage system, comprising:

a substrate layer;

select layer positioned above and not in the substrate layer;

a memory layer positioned above and not in the substrate layer, the memory layer includes;

a monolithic three dimensional array of memory elements,

word lines connected to the memory elements, groups of word lines are connected together, and

vertically oriented bit lines connected to the memory elements, the memory elements in combination with the vertically oriented bit lines and the word lines form a continuous mesh, the select layer includes select lines, the select layer includes a top row of vertically oriented select devices that are connected to the vertically oriented bit lines and a bottom row of vertically oriented select devices that are connected to the select lines, select devices of the top row of vertically oriented select devices are in series with select devise of the bottom row of vertically oriented select devices.

20. The non-volatile storage system of claim 19, wherein:

each select device of the top row of vertically oriented select devices includes two gate interfaces;

each select device of the bottom row of vertically oriented select devices includes two gate interfaces;

the select lines comprise a first plurality of select lines each connected to two gate interfaces of the top row of vertically oriented select devices and a second plurality of select lines each connected to two gate interfaces of the top row of vertically oriented select devices;

a particular vertically oriented bit line is put in communication with a particular global bit by turning on a first select device from the top row of select devices and a second select device from the bottom row of select devices such that the first select device is connected to the particular global bit and the second select device is connected to the particular vertically oriented bit line, first select device is connected to and in series with the second select device; and

turning on the first select device and the second select device includes selecting a first select line from the first plurality of select lines and a second select line from the second plurality of select lines, the first select line is on an opposite side of the first select device and the second select device as the second select line.