DEBUG STATE MACHINE CROSS TRIGGERING

• US 20120150474A1
• Filed: 12/29/2010
• Published: 06/14/2012
• Est. Priority Date: 12/09/2010
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Rentschler, Eric M., Kommrusch, Steven J., Cooper, Elizabeth M., Ennis, Stephen
• Application Number:
  US12/980,849
• Publication Number:
  US 20120150474A1
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544

Abstract

In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.

Claims

1. A method for performing debug operations in an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each debug circuit being integrated with a corresponding one of the plurality of electronic modules, the method comprising:

each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, wherein the first cross trigger signal indicates that a triggering event has not occurred;

each of the plurality of debug circuits determining whether the triggering event has occurred; and

in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.

2. The method of claim 1, wherein determining whether the triggering event has occurred comprises:

receiving one or more signals from one or more sources external to the first debug circuit, wherein the one or more signals are selected from a group consisting of a debug bus bit having a pre-defined state;

a debug bus bit transition occurring;

a trap signal;

a clock stop signal;

an error signal;

a performance monitor signal;

an interrupt;

a microcode-based trigger;

a breakpoint; and

a timer overflow;

determining whether the one or more signals have one or more pre-defined values or states; and

when the one or more signals have the one or more pre-defined values or states, determining that the triggering event has occurred.

3. The method of claim 1, wherein determining whether the triggering event has occurred comprises:

determining whether an internal triggering event has occurred, wherein the internal triggering event is selected from a group consisting of a counter matching a first value;

a clock count matching a second value;

trace data matching a third value;

trace data exceeding a fourth value;

debug data matching a fifth value;

a random event occurring; and

a flag being asserted.

4. The method of claim 1, further comprising:

each of the plurality of debug circuits detecting whether at least one other debug circuit of the plurality of debug circuits has produced the second cross trigger signal on the communications interface; and

each of the plurality of debug circuits performing an action in response to detecting that the at least one other debug circuit has produced the second cross trigger signal.

5. The method of claim 4, wherein detecting whether the at least one other debug circuit has produced the second cross trigger signal comprises:

detecting whether all other debug circuits of the plurality of debug circuits have produced the second cross trigger signal on the communications interface.

6. The method of claim 4, further comprising:

each of the plurality of debug circuits performing a mapping operation to determine the action.

7. The method of claim 4, wherein the action is selected from a group consisting of generating a core stop clock signal;

generating a die-wide stop clock signal;

generating a self refresh signal for a memory;

generating a communication interface receive disable signal;

generating a trace store signal;

generating a machine check exception (MCE) signal;

generating a debug event signal;

triggering a debug microcode interrupt; and

setting and clearing various bits in a register to be read by microcode upon the debug microcode interrupt.

8. The method of claim 1, wherein the plurality of electronic modules are included within an integrated circuit, the communications interface includes a cross trigger bus within the integrated circuit, wherein the cross trigger bus includes a plurality of conductors, and

wherein producing the first cross trigger signal comprises establishing a relatively high voltage signal on a conductor of the cross trigger bus, wherein each of the plurality of debug circuits produces the first cross trigger signal on a different conductor of the cross trigger bus, and

wherein producing the second cross trigger signal comprises establishing a relatively low voltage signal on the conductor of the cross trigger bus, wherein each of the plurality of debug circuits produces the second cross trigger signal on the different conductor of the cross trigger bus.

9. The method of claim 1, wherein the plurality of electronic modules are included within a plurality of integrated circuits of a multiple-chip module (MCM), the communications interface includes one or more pins of each of the integrated circuits and conductors between the one or more pins of the integrated circuits, and wherein the first cross trigger signal and the second cross trigger signal are produced on one or more of the pins of the integrated circuits.

10. The method of claim 1, wherein the plurality of electronic modules are included within a plurality of device packages installed in a plurality of sockets of the electronic system that are communicatively coupled through a printed circuit board, the communications interface includes one or more pins of each of the device packages and conductors on the printed circuit board between the plurality of sockets, and wherein the first cross trigger signal and the second cross trigger signal are produced on one or more of the pins of the device packages.

11. A method for performing debug operations in an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each debug circuit being integrated with a corresponding one of the plurality of electronic modules, the method performed by a debug circuit of the plurality of debug circuits and comprising:

producing a first cross trigger signal on a communications interface between the plurality of debug circuits, wherein the first cross trigger signal indicates that a triggering event has not occurred;

determining that the triggering event has occurred; and

in response to determining that the triggering event has occurred, producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.

12. The method of claim 11, further comprising:

detecting whether at least one other debug circuit of the plurality of debug circuits has produced the second cross trigger signal on the communications interface; and

performing an action in response to detecting that the at least one other debug circuit has produced the second cross trigger signal.

13. The method of claim 12, wherein detecting whether the at least one other debug circuit has produced the second cross trigger signal comprises:

detecting whether all other debug circuits of the plurality of debug circuits have produced the second cross trigger signal on the communications interface.

14. The method of claim 12, wherein the action is selected from a group consisting of generating a core stop clock signal;

generating a die-wide stop clock signal;

generating a self refresh signal for a memory;

generating a communication interface receive disable signal;

generating a trace store signal;

generating a machine check exception (MCE) signal;

generating a debug event signal;

triggering a debug microcode interrupt; and

setting and clearing various bits in a register to be read by microcode upon the debug microcode interrupt.

15. The method of claim 11, wherein the triggering event comprises one or more events selected from a group consisting of a counter matching a first value;

a clock count matching a second value;

trace data matching a third value;

trace data exceeding a fourth value;

debug data matching a fifth value;

a debug bus bit having a pre-defined state;

a debug bus bit transition occurring;

a random event occurring;

a flag being asserted; and

receiving one or more signals from one or more sources external to the second electronic module, wherein the one or more signals are selected from a group consisting of a second cross trigger signal on the communications interface;

a trap signal;

a clock stop signal;

an error signal;

a performance monitor signal;

an interrupt;

a microcode-based trigger;

a breakpoint and a timer overflow.

16. An electronic system comprising:

a first electronic module;

a second electronic module;

a first debug circuit integrated with the first electronic module, wherein the first debug circuit is configured to produce a first cross trigger signal on a communications interface between the first debug circuit and a second debug circuit, wherein the first cross trigger signal indicates that a triggering event has not occurred, and wherein the first debug circuit is further configured to determine whether the triggering event has occurred, and in response to determining that the triggering event has occurred, to produce a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred; and

the second debug circuit integrated with the second electronic module, wherein the second debug circuit is configured to produce the first cross trigger signal on the communications interface, wherein the first cross trigger signal indicates that the triggering event has not occurred, to determine whether the triggering event has occurred, and in response to determining that the triggering event has occurred, to produce the second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.

17. The electronic system of claim 16, wherein the first electronic module and the second electronic module are included within an integrated circuit, and the communications interface includes a cross trigger bus within the integrated circuit.

18. The electronic system of claim 17, wherein the cross trigger bus comprises a plurality of conductors arranged in a parallel configuration.

19. The electronic system of claim 16, wherein the first electronic module is included within a first integrated circuit of a multiple-chip module (MCM), the second electronic module is included within a second integrated circuit of the MCM, and the communications interface includes a die-to-die interface within the MCM.

20. The electronic system of claim 16, wherein the first electronic module is included within a first device package installable in a first socket of the electronic system, and the second electronic module is included within a second device package installable in a second socket of the electronic system that is communicatively coupled with the first socket, and the communications interface comprises at least a first pin of the first device package, a conductive path on a printed circuit board between the first socket and the second socket, and a second pin of the second device package.