Programmable Controller

• US 20120151153A1
• Filed: 07/03/2009
• Published: 06/14/2012
• Est. Priority Date: 07/03/2009
• Status: Abandoned Application

• Current Assignee: Axel Jantsch
• Original Assignee: Axel Jantsch
• Inventors: Zhonghai, Lu, Xiaowen, Chen, Hemani, Ahmed, Jantsch, Axel
• Application Number:
  US13/381,614
• Publication Number:
  US 20120151153A1
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 9/24 Loading of the microprogram

Abstract

A controller is provided which comprises one or more processors, a control store, a first interface control unit for interfacing a local core and a second interface control unit for interfacing one or more remote cores via an interconnect, wherein the processor/s discloses programmable mini-processor/s is adapted to execute, add, remove or modify a function by executing micro-code maintained typically in the local memory but also possibly in remote, or even off-chip memory, and obtained via the control store, in response to receiving a command from the first or the second interface control unit.

Claims

1. A controller comprising a processor, a control store, a first interface control unit for interfacing a local core and a second interface control unit for interfacing one or more remote cores via an interconnect,

wherein the processor is a programmable processor that is adapted to execute, add, remove or modify a function by executing associated micro-code that is obtained via the control store, in response to receiving a command from one of the interface control units.

2. A controller according to claim 1, wherein the command corresponds to an associated programmable micro-code.

3. A controller according to claim 1, wherein the micro-code corresponds to one or more executable micro-instructions.

4. A controller according to claim 3, wherein the executable micro-instructions are defined to implement or activate a specific function.

5. A controller according to claim 1, wherein the function is a memory management function which supports Distributed Shared Memory and/or Message Passing.

6. A controller according to claim 1 wherein the function is a function that relates to at least one of:

local and remote memory access, synchronisation, cache coherence, memory consistency, virtual-to-physical address translation.

7. A controller according to claim 1, wherein the first interface control unit and the second interface control unit are adapted to upload an executable micro-code from the local memory to the control store in response to having received a corresponding command at the respective interface control unit.

8. A controller according to claim 7, wherein the first interface control unit and the second first interface control unit further comprises a respective command look-up table, and wherein the control units are further adapted to determine whether an executable micro-code is available at the control store by checking the command look-up table.

9. A controller according to claim 8, wherein, for an executable micro-code, the command look-up table is adapted to comprise:

an identifier, which identifies a command, and a start address, which indicates where the micro-code associated with an identified command is located in the control store.

10. A controller according to claim 8, wherein the interface control units are adapted to upload executable micro-code to the control store from any of:

the local memory of the controller;

a memory of a remote node, or from an off-chip memory, in case the executable micro-code is not already stored at the control store.

11. A controller according to claim 8, wherein the first interface control unit is adapted to forward commands received from the main core of a first node and the second interface control unit is adapted to forward commands received from a node other than the first node.

12. A controller according to claim 8, wherein the controller comprises a first programmable processor, interconnected to the first interface control unit, and a second programmable processor, inter-connected to the second interface control unit.

13. A controller according to claim 8, wherein the first programmable processor and/or the second programmable processor is/are a mini-processor.

14. A controller according to claim 12, further comprising a synchronisation unit, adapted to coordinate the programmable processors, by serializing commands that are simultaneously requesting memory access to the same memory region.

15. An on-chip system, comprising at least two nodes, at least one of which is provided with a controller, according to claim 12.

16. A multi-core computing platform comprising at least two nodes, at least one of which is provided with a controller, according to claim 1].

17. A multi-core computer comprising at least two nodes, at least one of which is provided with a controller, according to claim 1.

18. A method at a controller, comprising a processor, a control store, a first interface control unit for interfacing a local core, and a second interface control unit for interfacing one or more remote cores via an interconnect wherein the following steps are performed at the processor, being a programmable processor:

receiving, from the first interface control unit or the second interface control unit, a command that triggers executing, adding, removing or modifying of a function at the controller,

obtaining, from the control store, micro-code corresponding to the command, and

executing the micro-code, such that the function is executed, added, removed or modified at the controller.

19. A method according to claim 18, wherein the microcode corresponds to one or more executable microinstructions.

20. A method according to claim 19, wherein the one or more executable micro-instructions are defined to implement a specific function.

21. A method according to claim 18, wherein the function is a memory management function which supports Distributed Shared Memory and/or Message Passing for inter-processing communication.

22. A method according to claim 18, wherein the obtaining step comprises the further step of:

uploading the one or more executable micro-code to the control store from any of;

the local memory of the controller;

a memory of a remote node, or from an offchip memory, in case the executable micro-code is not already stored in the control store.

23. A method according to claim 18, wherein the obtaining step comprises the further step of:

generating the one or more addresses required to fetch the relevant micro-instructions.

24. A method according to claim 18, comprising the further step of:

activating a replacement policy to replace micro-code presently stored in the control store with the micro-code corresponding to the command, in case there is no space available for uploading the micro-instructions to the control store.

25. A method according to claim 18, wherein the executing step comprises the step of executing a function relating to any of:

local and remote memory access;

synchronisation;

cache coherency;

memory consistency, or virtual-to-physical (V2P) address translation.

26. A method according to claim 18, wherein the executing step comprises the step of executing a function relating to any of:

open, close and query communication channel, send or receive a message.

27. A method according to claim 18, wherein the controller comprises a first programmable processor, inter-connected to the first interface control unit, and a second programmable processor, inter-connected to the second interface control unit, and wherein the method can be executed on any of the processors.

28. A method according to claim 18, further comprising a serializing step for serializing memory access requests in case different commands that are simultaneously requesting access to the same memory region are received by the controller, the serialization step being executed by a synchronisation unit.

29. A method according to claim 18, further comprising a determining step for determining whether an executable micro-code is available at the local control store by checking a command look-up table, the determining step being executed at the first interface control unit or the second first interface control unit.