ELECTRICAL CONNECTIVITY TEST APPARATUS AND METHODS

• US 20120151289A1
• Filed: 12/14/2010
• Published: 06/14/2012
• Est. Priority Date: 12/14/2010
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Rodriguez, Jose Miguel, West, Matthew James, Espasa, Cesar Fernandez
• Granted Patent: US 8,581,600 B2
• Time in Patent Office: Days
• US Class Current: 714/738
• CPC Class Codes: G01R 31/54 Testing for continuity

Abstract

Methods and apparatus are provided related to testing electrical connectivity. A sequence of distinct test data signal patterns is issued. The test data signals are propagated by way of respective pathways and electrical connectors. A feedback signal is generated in accordance with a test function for each of the test data signal patterns. A test results message is generated in accordance with the feedback signals, which can include specific diagnostic or identifying information.

Claims

1. An apparatus, comprising:

a plurality of drivers each configured to transmit data by way of a low-voltage differential signal;

a plurality of receivers each configured to receive a respective one of the low-voltage differential signals and to provide a corresponding single-ended output signal, the plurality of receivers coupled to the plurality of drivers by way of an electrical connector;

circuitry configured to provide a feedback signal by way of an electrical pathway, the feedback signal corresponding to a test function of the plurality of single-ended output signals; and

a controller configured to issue a connectivity test result message in accordance with the feedback signal.

2. The apparatus according to claim 1, the circuitry including:

a plurality of resistors each coupled to a common node and to a respective one of the single-ended output signals;

an analog-to-digital converter configured to provide a digital signal corresponding to an analog voltage present at the common node; and

circuitry configured to transmit a serial data representation of the digital signal thus defining the feedback signal.

3. The apparatus according to claim 1, the controller controller further configured to:

assert a test signal at a first logic level during a connectivity test sequence;

assert a plurality of test data signals in accordance with the connectivity test sequence, each of the test data signals formatted to be input to a respective one of the drivers, the connectivity test sequence defined by a plurality of distinct test data patterns; and

assert the test signal at a second logic level outside of the test sequence.

4. The apparatus according to claim 3, the test signal formatted to be input to a mode selector of a multiplexer.

5. The apparatus according to claim 1 further comprising a multiplexer configured to couple the plurality of drivers to respective ones of:

a plurality of data signals during a normal operating mode; and

a plurality of test data signals provided by the controller during a test sequence operating mode.

6. The apparatus according to claim 1, the circuitry further configured such that the test function is in accordance with:

Vcn=(n−

1)(Vh−

VI)/n+VI±

Vtol;

where;

Vcn=voltage at a common node;

n=number of the plurality of drivers;

Vh=greater logic level voltage;

VI=lesser logic level voltage; and

Vtol=tolerance window about an expected voltage.

7. The apparatus according to claim 1, the circuitry configured such that the feedback signal includes a serial data signal and a clock signal.

8. An electronic circuit configured to:

respectively assert a plurality of test data signals so as to define a unique pattern for each step of a test sequence;

receive a respective feedback signal for each step in the test sequence; and

provide a connectivity test result message in accordance with the feedback signals, the electronic circuit configured to evaluate the feedback signals in accordance with a tolerance.

9. The electronic circuit according to claim 8, further configured to:

assert a mode signal in a first logic state during the test sequence, the mode signal formatted to be input to a multiplexer; and

assert the mode signal in a second logic state outside of the test sequence.

10. The electronic circuit according to claim 8, further configured such that:

all of the test data signals are asserted to a first logic level during one step of the test sequence; and

one of the test data signals is asserted to a second logic level while all of the other test data signals are asserted to the first logic level during each of the other steps of the test sequence.

11. The electronic circuit according to claim 8, the electronic circuit being part of a printing apparatus.

12. The electronic circuit according to claim 8, the electronic circuit at least partially defined by an integrated circuit device.

13. The electronic circuit according to claim 8, further configured such that a total number of steps in the test sequence is one greater than a total number of the test data signals.

14. A method, comprising:

issuing a sequence of unique test patterns within an electronic circuit, each test pattern defined by a plurality of test data signals simultaneously asserted at respective logic levels;

propagating the test patterns through a plurality of drivers to a plurality of receivers by way of at least one electrical connector;

generating a serial data feedback signal for each of the test patterns in accordance with a test function;

evaluating each of the feedback signals; and

providing a test results message in accordance with the evaluating,

15. The method according to claim 14, the test function performed in accordance with:

Vcn(n−

1)*(Vh−

VI)/n+VI;

where;

Vcn=voltage at a common node;

n=number of the test data signals;

Vh=greater logic level voltage; and

VI=lesser logic level voltage.

16. The method according to claim 14, each of the drivers configured to receive a respective one of the test data signals and to transmit a corresponding low-voltage differential signal, each of the receivers configured to receive a respective one of the low-voltage differential signals and to provide a corresponding single-ended output signal.