NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION
First Claim
1. A field-effect-transistor (FET), comprising:
- a gate stack over a channel region;
source and drain regions next to said channel region; and
nickel-silicide formed on top of said source and drain regions,wherein said nickel-silicide contains platinum which has a platinum concentration level that is higher near a bottom surface than near a top surface of said nickel-silicide.
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Accused Products
Abstract
Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
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Citations
10 Claims
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1. A field-effect-transistor (FET), comprising:
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a gate stack over a channel region; source and drain regions next to said channel region; and nickel-silicide formed on top of said source and drain regions, wherein said nickel-silicide contains platinum which has a platinum concentration level that is higher near a bottom surface than near a top surface of said nickel-silicide. - View Dependent Claims (2, 3, 4)
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5. A field-effect-transistor (FET), comprising:
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a gate stack over a channel region; spacers adjacent to sidewalls of said gate stack; source and drain regions next to said channel region but separated by said spacers; and silicide formed at top of said source and drain regions, wherein said silicide is a platinum-containing nickel-silicide having a concentration level of platinum that is higher near a bottom surface than near a top surface of said silicide. - View Dependent Claims (6, 7)
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8. A field-effect-transistor (FET), comprising:
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a gate stack over a channel region inside a semiconductor substrate; spacers adjacent to sidewalls of said gate stack; source and drain regions, adjacent to said spacers, inside said substrate; and a silicide layer formed at a top portion of said source and drain regions, wherein said silicide layer has top surface and a bottom surface and is a platinum-containing nickel-silicide having a concentration level of platinum that is higher near said bottom surface than near said top surface of said silicide layer. - View Dependent Claims (9, 10)
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Specification