SEMICONDUCTOR COMPONENT WITH A SPACE SAVING EDGE STRUCTURE

• US 20120153386A1
• Filed: 12/19/2011
• Published: 06/21/2012
• Est. Priority Date: 08/03/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Siemieniec, Ralf, Blank, Oliver, Geissler, Christian, Roesch, Maximilian
• Granted Patent: US 9,252,251 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

Claims

1. Semiconductor component comprising:

a semiconductor body comprising a first side and a second side, and a first semiconductor layer having a basic doping of a first conductivity type;

at least one active component zone of a second conductivity type, which is complementary to the first conductivity type, in the first semiconductor layer;

a cell array with a plurality of trenches, each trench including a field electrode and a field electrode dielectric;

at least one cell array edge zone of the second conductivity type, the cell array edge zone in the cell array only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

2. The semiconductor device of claim 1, wherein a plurality of distant cell array edge zones are arranged below the at least one trench of the cell array.

3. The semiconductor device of claim 1,

wherein the semiconductor body comprises an inner region and an edge region,

wherein the first semiconductor layer extends across the inner region and the edge region, and

wherein the at least one active component zone is only in the inner region.

4. The semiconductor device of claim 3, further comprising:

an edge structure in the edge region.

5. The semiconductor device of claim 4, wherein the edge structure comprises:

at least one edge trench extending from the first side into the semiconductor body;

a dielectric layer in the edge region; and

a first edge zone of the second conductivity type adjoining the edge trench and being at least partially disposed below the trench.

6. The semiconductor component of claim 5,

wherein the at least one cell array edge zone adjoins one edge zone in the lateral direction of the semiconductor body.

7. The semiconductor component of claim 1,

wherein the cell array includes an outermost trench adjacent the at least one edge trench, and

wherein the at least one cell array edge zone adjoins the outermost trench of the cell array.

8. The semiconductor component of claim 7,

wherein the outermost trench is ring-shaped and terminates the cell array in a lateral direction of the semiconductor body.

9. The semiconductor component of claim 1,

wherein the edge region of the cell array extends along an edge of the cell array and has a size of between 0.1% and 2% of a size of the cell array in a horizontal plane of the semiconductor body.

10. The semiconductor component of claim 1,

wherein the cell array edge zone is ring-shaped in a horizontal plane of the semiconductor body.

11. The semiconductor component of claim 1,

wherein the at least one cell array edge zone is distant to the edge zone.

12. The semiconductor component of claim 1, further comprising:

at least two cell array edge zones that are distant in a lateral direction of the semiconductor body.

13. The semiconductor component of claim 12,

wherein the at least two cell array edge zones are ring-shaped in a horizontal plane of the semiconductor body.

14. The semiconductor component of claim 1, further comprising:

an edge electrode in the at least one edge trench, the edge electrode separated from the semiconductor body by the dielectric layer.

15. The semiconductor body of claim 1,

wherein the edge trench is completely filled with the dielectric layer.

16. The semiconductor component of claim 1, further comprising:

a second edge zone of the second conductivity type separated from the first edge zone, laterally adjoining the at least one edge trench and adjoining the first side.

17. The semiconductor component of claim 1, wherein the first edge zone has a doping concentration such that it can be completely depleted or can be depleted except for an area having dimensions smaller than a lateral width of the edge trench when the semiconductor device is in an off-state

18. The semiconductor component of claim 1, wherein the cell array edge zone has a doping concentration such that it can be completely depleted or can be depleted except for an area having dimensions smaller than a lateral width of the edge trench when the semiconductor device is in an off-state.

19. The semiconductor component of claim 1, implemented as a MOS transistor and comprising in the inner region a plurality of transistor cells, each transistor cell comprising:

a source zone of a first conductivity type, a drift zone of the first conductivity type, and a body zone of the second conductivity type between the source zone and the drift zone;

a gate electrode being disposed adjacent to the body zone and being insulated against the body zone by a gate dielectric.

20. The semiconductor component of claim 19, the gate electrodes of the transistor cells are arranged in the same trenches as the field electrodes, the field electrodes extending deeper into the semiconductor body than the gate electrodes.

21. The semiconductor component of claim 14, wherein the edge electrode is electrically coupled to a semiconductor zone doped complementary to a basic doping of the semiconductor layer and arranged between the at least one edge trench and the inner region.

22. The semiconductor component of claim 21, wherein the semiconductor zone adjoins the at least one edge trench.

23. The semiconductor component of claim 1, further comprising:

at least two edge trenches, the trenches being disposed distant to each other in a lateral direction of the semiconductor body;

a number of first edge zones corresponding to the number of trenches.

24. The semiconductor component of claim 23, comprising a number of second edge zones corresponding to the number of trenches, with each of the second edge zones adjoining one edge trench in a direction opposite to the direction of the inner region.

25. The semiconductor component of claim 24, wherein each of the second edge zones are disposed between two edge trenches and extend in a lateral direction from trench to trench.

26. The semiconductor device of claim 1, wherein the semiconductor layer comprises a first partial layer and a second partial layer below the first partial layer and having a lower doping concentration than the first partial layer.

27. The semiconductor device of claim 26, wherein the plurality of trenches of the cell array extends into the second partial layer.