Encapsulation of Closely Spaced Gate Electrode Structures

• US 20120153398A1
• Filed: 12/21/2010
• Published: 06/21/2012
• Est. Priority Date: 12/21/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Baars, Peter, Carter, Richard, Wei, Andy
• Granted Patent: US 8,647,952 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.

Claims

1. A method, comprising:

forming a first gate electrode structure and a second gate electrode structure above a semiconductor substrate;

forming a first layer of a first dielectric material adjacent to or in contact with sidewalls of each of said first and second gate electrode structures;

forming a second layer of a second dielectric material on said first layer; and

forming a third layer of a third dielectric material on said second layer, wherein forming said third layer further comprises forming a first horizontal portion of said third layer above a surface of said semiconductor substrate between said first and second gate electrode structures.

2. The method of claim 1, wherein forming said first and second gate electrode structures comprises forming said first gate electrode structure adjacent to said second gate electrode structure and having a gate electrode pitch of less than 100 nm.

3. The method of claim 1, further comprising forming a cap layer comprising a fourth dielectric material above each of said first and second gate electrode structures prior to forming said first layer.

4. The method of claim 3, wherein forming said third layer further comprises forming a second horizontal portion of said third layer above said cap layer.

5. The method of claim 1, further comprising performing at least one etching process to define an opening in said first horizontal portion of said third layer to expose a surface of said semiconductor substrate.

6. The method of claim 5, further comprising forming a conductive material in said opening.

7. The method of claim 1, wherein each of said first, second and third dielectric materials comprise a same dielectric material.

8. A method, comprising:

forming a plurality of first gate electrode structures in and above a first active region of a semiconductor substrate;

forming a plurality of second gate electrode structures above a second active region of said semiconductor substrate;

forming a first layer of a first dielectric material above said first and second active regions of said semiconductor substrate, wherein at least a first portion of said first layer covers sidewall surfaces of each of said first and second gate electrode structures;

forming a second layer of a second dielectric material above said first layer, wherein at least a first portion of said second layer covers said first portion of said first layer; and

forming a third layer of a third dielectric material above said first and second layers, wherein at least a first portion of said third covers said first portions of said first and second layers.

9. The method of claim 8, wherein forming at least two of each of said plurality of first and second gate electrode structures comprises forming a cap layer comprising a fourth dielectric material above a gate electrode material.

10. The method of claim 8, wherein forming at least one of each of said plurality of first and second gate electrode structures comprises forming a dielectric material liner on said sidewall surfaces thereof.

11. The method of claim 8, wherein forming at least one of said first, second and third layers comprises performing a conformal material deposition process.

12. The method of claim 8, wherein each of said first, second and third dielectric materials comprise a same dielectric material.

13. The method of claim 12, wherein said same dielectric material exhibits an etch selectivity relative to a dielectric fill material comprising a metallization layer formed above at least one of each of said plurality of first and second gate electrode structures.

14. The method of claim 8, further comprising performing an epitaxial deposition process to selectively form an epitaxial semiconductor material to a height above an upper surface of said second active region adjacent to at least one of said plurality of second gate electrode structures and forming said second layer of said dielectric material above said epitaxial semiconductor material.

15. The method of claim 14, wherein selectively forming said epitaxial semiconductor material comprises exposing at least a portion of said upper surface of said second active region by selectively removing said first layer formed thereabove.

16. The method of claim 15, further comprising forming at least one cavity in said second active region adjacent at least one of said plurality of second gate electrode structures prior to selectively forming said epitaxial semiconductor material.

17. The method of claim 8, further comprising performing an epitaxial deposition process to selectively form an epitaxial semiconductor material to a height above an upper surface of said first active region adjacent to at least one of said plurality of first gate electrode structures and forming said third layer above said epitaxial semiconductor material.

18. A semiconductor device, comprising:

a plurality of NMOS transistor elements, wherein each of said plurality of NMOS transistor elements comprises a first gate electrode structure above a first active region of a semiconductor substrate, at least two of said plurality of first gate electrode structures comprise a first encapsulating stack, said first encapsulating stack comprises a first dielectric cap layer and a first sidewall spacer stack, and said first sidewall spacer stack comprises at least three separately formed dielectric material layers; and

a plurality of PMOS transistor elements, wherein each of said plurality of PMOS transistor elements comprises a second gate electrode structure above a second active region of said semiconductor substrate, at least two of said plurality of second gate electrode structures comprise a second encapsulating stack, said second encapsulating stack comprises a second dielectric cap layer and a second sidewall spacer stack, and said second sidewall spacer stack comprises at least three separately formed dielectric material layers.

19. The semiconductor device of claim 18, wherein said first and second dielectric cap layers and each of said at least three separately formed dielectric material layers of each of said first and second sidewall spacer stacks comprise a same dielectric material.

20. The semiconductor device of claim 18, wherein a thickness of at least one of said first and second sidewall spacer stacks is approximately 10-16 nm.

21. The semiconductor device of claim 18, further comprising an additional dielectric material layer above at least one of each of said first and second cap layers of each of said plurality of first and second gate electrode structures, respectively.

22. The semiconductor device of claim 21, wherein a combined thickness of said at least one of said first and second cap layers and said additional dielectric material layer thereabove is approximately 35-40 nm.

23. The semiconductor device of claim 18, further comprising raised source and drain regions formed in an active region adjacent at least one of said plurality of transistor elements, said raised source and drain regions comprising an epitaxial semiconductor material.

24. The semiconductor device of claim 23, wherein at least one of said raised source and drain regions is formed in at least one cavity in said active region adjacent to said at least one of said plurality of transistor elements.

25. A semiconductor device, comprising:

a first gate electrode structure above an active region of a semiconductor substrate;

a second gate electrode structure above said active region and adjacent to said first gate electrode structure, wherein each of said first and second gate electrode structures comprise;

a gate electrode material;

a dielectric cap layer above said gate electrode material;

a first layer of a first dielectric material adjacent to or in contact with sidewalls of said gate electrode material;

a second layer of a second dielectric material on said first layer; and

a third layer of a third dielectric material on said second layer, wherein said third layer further comprises a first horizontal portion above said active region between said first and second gate electrode structures, said first horizontal portion comprises an opening, and said opening exposes said active region; and

a conductive material in said opening, wherein said conductive material contacts said exposed active region.

26. The semiconductor device of claim 25, wherein said first and second gate electrode structures have a pitch dimension less than 100 nm.

27. The semiconductor device of claim 25, wherein said dielectric cap layer and said first second and third dielectric materials comprise a same dielectric material.