HYBRID SUBSTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES

• US 20120153445A1
• Filed: 08/03/2011
• Published: 06/21/2012
• Est. Priority Date: 12/15/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Daewoo, Kim, Chulwoo
• Granted Patent: US 8,836,149 B2
• Time in Patent Office: Days
• US Class Current: 257/668
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 3/4614 : the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/4626 : characterised by the insulating layers or materials H05K3/4688 takes precedence

Abstract

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

Claims

1. A semiconductor package comprising:

a semiconductor chip including a plurality of chip pads having a first pitch; and

a substrate including a first conductive pattern connected to the chip pads, and a second conductive pattern connected to an external terminal and electrically connected to the first conductive pattern, wherein the first conductive pattern has the first pitch, and the second conductive pattern has a second pitch greater than the first pitch.

2. The semiconductor package of claim 1, wherein the substrate comprises:

a first surface on which the semiconductor chip is mounted; and

a second surface opposite to the first surface, the external terminal connected to the second surface, wherein the first surface of the substrate includes the first conductive pattern with the first pitch thereon, and the second surface of the substrate includes the second conductive pattern with the second pitch thereon.

3. The semiconductor package of claim 1, wherein the substrate comprises:

an organic substrate having the second conductive pattern; and

an inorganic layer on the organic substrate, the inorganic layer including the first conductive pattern.

4. The semiconductor package of claim 3, wherein the inorganic layer comprises:

a top surface facing the semiconductor chip; and

a bottom surface facing the organic substrate, wherein the first conductive pattern is on the top surface of the inorganic layer, and a third conductive pattern is on the bottom surface of the inorganic layer, the third conductive pattern having the second pitch, the third conductive pattern being connected to the first conductive pattern and the second conductive pattern.

5. The semiconductor package of claim 4, wherein the substrate further comprises:

a second organic substrate on the organic substrate, wherein the second organic substrate is electrically connected to the second conductive pattern and includes a fourth conductive pattern having a third pitch greater than the second pitch.

6. The semiconductor package of claim 1, wherein the substrate includes

an organic substrate including the second conductive pattern, and

an organic layer on the organic substrate, the organic layer including the first conductive pattern.

7. The semiconductor package of claim 6, wherein the organic layer includes a flexible film on which the first conductive pattern is disposed, the flexible film comprising a plurality of vias having the second pitch, the plurality of vias electrically connecting the first conductive pattern to the second conductive pattern.

8. The semiconductor package of claim 7, wherein the flexible film includes a polymer film.

9. The a semiconductor package of claim 7, wherein the organic substrate includes

a top surface on which the flexible film is disposed,

a bottom surface on which the second conductive pattern is disposed, and

a metal pattern having the second pitch on the top surface of the organic substrate, wherein the metal pattern is connected to the second conductive pattern and the plurality of vias, the metal pattern being aligned with the plurality of vias.

10-22. -22. (canceled)

23. A hybrid substrate comprising:

an insulation layer including a top surface, a bottom surface opposite to the top surface, and a conductive pattern having different pitches; and

an organic layer on the bottom surface of the insulation layer, the organic layer including a circuit pattern connected to the conductive pattern,

wherein the conductive pattern includes

a first metal pattern having a first pitch on the top surface of the insulation layer, and

a second conductive pattern having a second pitch greater than the first pitch connected to the circuit pattern, the second conductive pattern extending from the first metal pattern and penetrating through the insulation layer.

24. The hybrid substrate of claim 23, wherein the insulation layer includes one of an organic layer and an inorganic layer.

25. A hybrid substrate comprising:

a first insulation layer having a top surface and a bottom surface, the top surface including a first metal pattern having a first pitch and the bottom surface including a second metal pattern having a second pitch larger than the first pitch, the first insulation layer further including an intermediate pattern extending through the first insulation layer to electrically connect the first metal pattern to the second metal pattern; and

a second insulation layer on the bottom surface of the first insulation layer, the second insulation layer including a circuit pattern electrically connected to the second metal pattern, wherein the second insulation layer is comprised of an organic material.

26. The hybrid substrate of claim 25, wherein the first insulation layer is an inorganic layer.

27. The hybrid substrate of claim 26, wherein the intermediate pattern includes an internal pattern and a plurality of vias above and below the internal pattern.

28. The hybrid substrate of claim 26, wherein the circuit pattern includes a plurality of vias extending through the second insulation layer, the plurality of vias being spaced at the second pitch.

29. The hybrid substrate of claim 26, wherein the second insulation layer further includes a plurality of substrate pads attached to the plurality of vias.

30. The hybrid substrate of claim 25, wherein the first insulation layer is an organic layer.

31. The hybrid substrate of claim 30, wherein the intermediate pattern is a plurality of vias extending through the first layer and being spaced apart at the second pitch.

32. The hybrid substrate of claim 31, wherein the plurality of vias are arranged over the circuit pattern.

33. The hybrid substrate of claim 25, wherein the first insulation layer has a thickness of about 20 μ

m or less.