HYBRID FAST-SLOW PASSGATE CONTROL METHODS FOR VOLTAGE REGULATORS EMPLOYING HIGH SPEED COMPARATORS

• US 20120153909A1
• Filed: 08/19/2011
• Published: 06/21/2012
• Est. Priority Date: 12/16/2010
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bulzacchelli, John F., Toprak-Deniz, Zeynep, Friedman, Daniel J., Iadanza, Joseph A., Rasmus, Todd M., Bucossi, William L., Chhabra, Mohak
• Application Number:
  US13/213,368
• Publication Number:
  US 20120153909A1
• Time in Patent Office: Days
• US Class Current: 323/271
• CPC Class Codes: H02M 1/15 using active elements
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence
• CPC Class Codes: H02M 3/1566 with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation

Abstract

Voltage regulator circuits and methods implementing hybrid fast-slow passgate control circuitry are provided to minimize the ripple amplitude of a regulated voltage output. In one aspect, a voltage regulator circuit includes a comparator, a first passgate device, a second passgate device, and a bandwidth limiting control circuit. The comparator compares a reference voltage to a regulated voltage at an output node of the voltage regulator circuit and generates a first control signal on a first gate control path based on a result of the comparing. The first and second passgate devices are connected to the output node of the regulator circuit. The first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node. The bandwidth limiting control circuit has an input connected to the first gate control path and an output connected to the second passgate device. The bandwidth limiting control circuit generates a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.

Claims

1. A voltage regulator circuit, comprising:

a comparator for comparing a reference voltage to a regulated voltage at an output node of the voltage regulator circuit and generating a first control signal on a first gate control path based on a result of the comparing;

a first passgate device connected to the output node, wherein the first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node;

a second passgate device connected to the output node; and

a bandwidth limiting control circuit having an input connected to the first gate control path and an output connected to the second passgate device, the bandwidth limiting control circuit generating a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.

2. The voltage regulator of claim 1, wherein the bandwidth limiting control circuit comprises a buffer and a low pass RC filter network.

3. The voltage regulator of claim 2, wherein the buffer is an inverter.

4. The voltage regulator circuit of claim 3, wherein an input of the inverter is connected to the first gate control path and receives as input an inverted first control signal from the first gate control path and outputs a similar version of the first control signal to the RC filter network, and wherein the RC filter network filters the similar version of the first control signal to generate the second control signal.

5. The voltage regulator circuit of claim 2, wherein a capacitor of the RC filter network is implemented by a parasitic capacitance of the second passgate device.

6. The voltage regulator circuit of claim 1, wherein the bandwidth limiting control circuit comprises a current starved inverter.

7. An integrated circuit chip, comprising:

a power grid;

a load circuit connected to the power grid; and

a distributed voltage regulator system comprising a plurality of voltage regulator circuits, each voltage regulator circuit generating a regulated voltage at an output node of the voltage regulator circuit, each output node connected to a different point on the power grid to supply a regulated voltage to the load circuit,

wherein each voltage regulator circuit comprises;

a comparator for comparing a reference voltage to the regulated voltage at the output node of the voltage regulator circuit and generating a first control signal on a first gate control path based on a result of the comparing;

a first passgate device connected to the output node, wherein the first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node;

a second passgate device connected to the output node; and

a bandwidth limiting control circuit having an input connected to the first gate control path and an output connected to the second passgate device, the bandwidth limiting control circuit generating a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.

8. The integrated circuit chip of claim 7, wherein the bandwidth limiting control circuit comprises a buffer and a low pass RC filter network.

9. The integrated circuit chip of claim 8, wherein the buffer is an inverter.

10. The integrated circuit chip of claim 9, wherein an input of the inverter is connected to the first gate control path and receives as input an inverted first control signal from the first gate control path and outputs a similar version of the first control signal to the RC filter network, wherein the RC filter network filters the similar version of the first control signal to generate the second control signal.

11. The integrated circuit chip of claim 8, wherein a capacitor of the RC filter network is implemented by a parasitic capacitance of the second passgate device.

12. The integrated circuit chip of claim 7, wherein the bandwidth limiting control circuit comprises a current starved inverter.

13. An integrated circuit chip, comprising:

a power grid;

a load circuit connected to the power grid; and

a distributed voltage regulator system comprising a plurality of voltage regulator circuits, each voltage regulator circuit generating a regulated voltage at an output node of the voltage regulator circuit, each output node connected to a different point on the power grid to supply the regulated voltage to the load circuit,

wherein the voltage regulator circuits comprise at least one master voltage regulator and one or more slave voltage regulator circuits,

wherein the at least one master voltage regulator comprises;

a comparator for comparing a reference voltage to the regulated voltage at the output node of the voltage regulator circuit and generating a first control signal on a first gate control path based on a result of the comparing;

a first passgate device connected to the output node, wherein the first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node;

a second passgate device connected to the output node;

a bandwidth limiting control circuit having an input connected to the first gate control path and an output connected to the second passgate device, the bandwidth limiting control circuit generating a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node, and

wherein each of the one or more slave voltage regulator circuits comprises;

a comparator for comparing a reference voltage to the regulated voltage at the output node of the voltage regulator circuit and generating a first control signal on a first gate control path based on a result of the comparing;

a first passgate device connected to the output node, wherein the first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node;

a second passgate device having an output connected to the output node of the slave voltage regulator and having an input connected to the bandwidth limiting control circuit of the master voltage regulator, wherein the second control signal generated by the bandwidth limiting control circuit of the master voltage regulator drives the second passgate of each slave voltage regulator circuit.

14. The integrated circuit chip of claim 13, wherein the bandwidth limiting control circuit of the at least one master voltage regulator comprises a current starved inverter.

15. A method for regulating voltage, comprising:

controlling a first passgate device in a bang-bang mode of operation using a first control signal generated on a first gate control path, to output current from the first passgate to a regulated voltage node; and

controlling a second passgate device, connected in parallel to the first passgate device, using a second control signal generated on a second gate control path, to output current from the second passgate to the regulated voltage node, wherein the second control signal is a slew rate limited version of the first control signal.

16. The method of claim 15, comprising generating the second control signal by receiving a complementary first control signal from the first gate control path, inverting the complementary signal to output a similar version of the first control signal on the second gate control path and low pass filtering the similar version of the first control signal to generate the second control signal.

17. The method of claim 15, comprising generating the second control signal by receiving a signal from the first gate control path, buffering the signal from the first gate control path to output a similar version of the first control signal on the second gate control path and low pass filtering the similar version of the first control signal to generate the second control signal.

18. The method of claim 15, comprising generating the second control signal by receiving a complementary first control signal from the first gate control path, applying the complementary first control signal to the input of a current starved inverter, and generating the second control signal at the output of the current starved inverter on the second gate control path.