MULTI PHASE CLOCK AND DATA RECOVERY SYSTEM

• US 20120154059A1
• Filed: 12/15/2011
• Published: 06/21/2012
• Est. Priority Date: 12/17/2010
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: den Besten, Gerrit Willem, van der Wel, Arnoud Pieter
• Application Number:
  US13/327,601
• Publication Number:
  US 20120154059A1
• Time in Patent Office: Days
• US Class Current: 331/34
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A multi-phase clock and data recovery circuit system including a voltage controlled oscillator including plural identical structural cells coupled in a ring, the voltage controlled oscillator providing plural phased shifted signals having the same frequency. The circuit further includes a feedback loop including plural data samplers adapted to receive the plural phase shifted signals provided by the voltage controlled oscillator and a phase detector coupled to coupled to a phase alignment circuit receiving output signals generated by the plural data samplers and generating control signals to the voltage controlled oscillator at a bit rate of the input signal.

Claims

1. A multi-phase clock and data recovery circuit system comprising:

a voltage controlled oscillator including a plurality of identical structural cells coupled in a ring, the voltage controlled oscillator providing a plurality of phased shifted signals having the same frequency; and

a feedback loop including;

a plurality of data samplers adapted to receive the plurality of phase shifted signals provided by the voltage controlled oscillator; and

a phase detector coupled to a phase alignment circuit receiving output signals generated by the plurality of data samplers and generating control signals to the voltage controlled oscillator at a bit rate of the input signal.

2. A multi-phase clock and data recovery circuit system as claimed in claim 1, wherein the plurality of phase shifted signals comprises a first set of signals and a second set of signals, coupled in pairs, each signal of the first set having a corresponded quadrature signal in the second set.

3. A multi-phase clock and data recovery circuit system of claim 2, wherein each signal of the first set of signals and the second set of signals are inputted to a respective second set of data samplers and a third set of data samplers.

4. A multi-phase clock and data recovery circuit system as claimed in claim 2, wherein the data samplers comprise one hot data samplers.

5. A multi-phase clock and data recovery circuit system as claimed in claim 4, wherein the one hot data samplers comprise one of T latches and T flip-flops generating T-aligned signals.

6. A multi-phase clock and data recovery circuit system as claimed in claim 5 wherein the phase detector receives a combination of the T-aligned signals.

7. A method for a multi-phase clock and data recovery circuit comprising steps of;

providing a first plurality of phased shifted signals having a same frequency;

providing a feedback loop including;

a plurality of data samplers adapted to receive the plurality of phase shifted signals provided by the voltage controlled oscillator; and

a phase detector coupled to a phase alignment circuit receiving output signals generated by the plurality of data samplers and generating control signals to the voltage controlled oscillator at a bit rate of the input signal.