Voltage Level Control Circuit and Associated Method

• US 20120154680A1
• Filed: 12/12/2011
• Published: 06/21/2012
• Est. Priority Date: 12/17/2010
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Chen, Chien-Hung, Wu, Shao-Chih, Wong, Wei-Shu
• Granted Patent: US 8,937,684 B2
• Time in Patent Office: Days
• US Class Current: 348/521
• CPC Class Codes: H04N 5/08 Separation of synchronising signals from picture signals

Abstract

A voltage level control circuit controls a target slicing voltage level to slice a video signal by a target circuit. The voltage level control circuit includes a slicing circuit for sequentially slicing the video signal by a plurality of slicing voltage levels to correspondingly generate a plurality of first clock signals; a detection circuit for respectively detecting a plurality of phase differences between the first clock signals and a plurality of corresponding second clock signals to generate a plurality of detection signals; an oscillating circuit for generating the second clock signals according to the detection signals, respectively; and an adjusting circuit for determining whether to adjust the target slicing voltage level according to the detection signals corresponding to the slicing voltage levels.

Claims

1. A voltage level control circuit, for controlling a target slicing voltage level used to slice a video signal by a target circuit, the voltage level control circuit comprising:

a slicing circuit, for slicing the video signal by sequentially adopting a plurality of slicing voltage levels to correspondingly generate a plurality of first clock signals;

a detection circuit, for respectively detecting a plurality of phase differences between the first clock signals and a plurality of second clock signals to generate a plurality of detection signals;

an oscillating circuit, for generating the second clock signals according to the detection signals, respectively; and

an adjusting circuit, determining whether to adjust the target slicing voltage level according to the detection signals corresponding to the slicing voltage levels.

2. The voltage level control circuit as claimed in claim 1, wherein the adjusting circuit comprises:

a phase difference accumulator, for accumulating the phase differences between the first clock signals and the second clock signals according to the detection signals to respectively generate a plurality of phase difference accumulation results corresponding to the slicing voltage levels; and

a determining circuit, for generating an adjustment signal to the target circuit according to the phase difference accumulation results and a specific phase difference accumulation value to determine whether to adjust the target slicing voltage level, wherein the specific phase difference accumulation value corresponds to the target slicing voltage level currently implemented by the target circuit.

3. The voltage level control circuit as claimed in claim 2, wherein the adjusting circuit further comprises:

a limitation circuit, coupled between the detection circuit and the phase difference accumulator, for adjusting one of the phase differences corresponding to the detection signals to a predetermined phase difference when the phase difference is larger than a predetermined upper limit value.

4. The voltage level control circuit as claimed in claim 2, wherein the determining circuit compares the phase difference accumulation results to select a specific phase difference accumulation result, compares the specific phase difference accumulation result with the specific phase difference accumulation value to generate a comparison result, and selectively generates the adjustment signal according to the comparison result.

5. The voltage level control circuit as claimed in claim 4, wherein the specific phase difference accumulation result is a minimum phase difference accumulation result of the phase difference accumulation results.

6. The voltage level control circuit as claimed in claim 4, wherein the determining circuit calculates a difference between the specific phase difference accumulation result and the specific phase difference accumulation value, and compares the difference with a predetermined threshold value to generate the comparison result.

7. The voltage level control circuit as claimed in claim 1, wherein the video signal is a composite video blanking sync signal.

8. The voltage level control circuit as claimed in claim 7, wherein the target slicing voltage level is for slicing horizontal synchronization signal components of the composite video blanking sync signal.

9. A voltage level control method, for controlling a target slicing voltage level used to slice a video signal by a target circuit, the voltage level control method comprising:

(a) slicing via a slicing circuit the video signal by sequentially implementing a plurality of slicing voltage levels to correspondingly generate a plurality of first clock signals;

(b) respectively detecting a plurality of phase differences between the first clock signals and a plurality of corresponding second clock signals to generate a plurality of detection signals;

(c) respectively generating the second clock signals according to the detection signals; and

(d) determining whether to adjust the target slicing voltage level according to the detection signals corresponding to the slicing voltage levels.

10. The voltage level control method as claimed in claim 9, wherein Step (d) comprises:

(e) accumulating the phase differences between the first clock signals and the second clock signals according to the detection signals to respectively generate a plurality of phase difference accumulation results corresponding to the slicing voltage levels; and

(f) generating an adjustment signal according to the phase difference accumulation results and a specific phase difference accumulation value to determine whether to adjust the target slicing voltage level, wherein the specific phase difference accumulation value corresponds to the target slicing voltage level currently implemented by the target circuit.

11. The voltage level control method as claimed in claim 10, wherein Step (d) further comprises:

adjusting one of the phase differences to a predetermined phase difference when the phase difference is higher than a predetermined upper limit value.

12. The voltage level control method as claimed in claim 10, wherein Step (f) comprises:

(g) comparing the phase difference accumulation results to select a specific phase difference accumulation result;

(h) comparing the specific phase difference accumulation result with the specific phase difference accumulation value to generate a comparison result; and

(i) selectively generating the adjustment signal according to the comparison result.

13. The voltage level control method as claimed in claim 12, wherein the specific phase difference accumulation result is a minimum phase accumulation result of the phase difference accumulation results.

14. The voltage level control method as claimed in claim 12, wherein Step (h) comprises:

calculating a difference between the specific phase difference accumulation result and the specific phase difference accumulation value; and

comparing the difference with a predetermined threshold value to generate the comparison result.

15. The voltage level control method as claimed in claim 9, wherein the video signal is a composite video blanking sync signal.

16. The voltage level control method as claimed in claim 15, wherein the target slicing voltage level is for slicing horizontal synchronization signal components of the composite video blanking sync signal.