ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT
First Claim
1. An integrated circuit device having an adaptive electrostatic discharge (ESD) protection, comprising:
- an external connection pin to be protected from ESD;
an external ground connection pin;
an adaptive electrostatic discharge (ESD) protection circuit comprising;
an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground;
a resistor coupled between a gate of the NMOS transistor and ground;
a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground;
a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.
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Accused Products
Abstract
For adaptive electrostatic discharge (ESD) protection, an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, has an external connection pin to be protected from ESD; an external ground connection pin; an adaptive electrostatic discharge (ESD) protection circuit having: an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground; a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.
18 Citations
38 Claims
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1. An integrated circuit device having an adaptive electrostatic discharge (ESD) protection, comprising:
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an external connection pin to be protected from ESD; an external ground connection pin; an adaptive electrostatic discharge (ESD) protection circuit comprising; an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground; a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A motor vehicle comprising
a data bus selected from the group consisting of a Local Interconnect Network (LIN) bus and a Controller Area Network (CAN) bus; an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, the integrated circuit device comprising; a data bus interface coupled via an external connection pin with said data bus; a circuit function coupled to the data bus interface; an external ground connection pin; an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first capacitor having a first terminal connected to the external connection pin; a first P-metal oxide semiconductor (PMOS) transistor having a drain connected to the second terminal, a source and bulk connected to the gate of the NMOS transistor and a gate connected to ground; a second PMOS transistor having a source and bulk connected to the gate of the NMOS transistor and a drain connected to ground; and a filter comprising a second resistor connected between the second terminal of the first capacitor and a gate of the second PMOS transistor and a second capacitor connected between the source and the gate of the second PMOS transistor.
Specification