SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20120155186A1
• Filed: 12/12/2011
• Published: 06/21/2012
• Est. Priority Date: 12/20/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chokan, Tomohito, Sudou, Naoaki
• Granted Patent: US 8,625,355 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A semiconductor memory device operate during a program verification operation to apply a read voltage to a word line and a pre-charge voltage to a bit line in order to provide output data. A number of fail cells is determined in view of the output data, wherein the number of fail cells is directly related to an increase in voltage on a common source line (CSL) connected to memory cells providing the output data. During a subsequent program verification operation, the level of at least one of the read voltage and the pre-charge voltage is adjusted in response to the number of fail cells.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory strings, each memory string including memory cells series-connected between a string select transistor and a ground select transistor, wherein the around select transistor is connected to a common source line (CSL);

a plurality of word lines including a selected word line, wherein the selected word line is commonly connected to gates of a row of memory cells extending across the plurality of memory strings;

a plurality of bit lines including a selected bit line, wherein each one of the plurality of bit lines is connected to a corresponding one of the plurality of memory strings;

a page buffer that provides output data from selected memory cells associated with at least one of the selected word line and the selected bit line during a verify read operation;

a fail bit counter that determines a number of fail cells among the selected memory cells;

a voltage controller that generates a read voltage applied to the selected word line during the verify read operation and a pre-charge voltage applied to selected bit line during the read verify operation; and

a control circuit that controls the voltage controller in response to the number of fail cells.

2. The semiconductor memory device of claim 1, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the pre-charge voltage in response to the number of fail cells.

3. The semiconductor memory device of claim 1, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the read voltage in response to the number of fail cells.

4. The semiconductor memory device of claim 1, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the pre-charge voltage and the read voltage in response to the number of fail cells.

5. The semiconductor memory device of claim 1, wherein the control circuit stores a number of inhibit cells and controls the voltage controller in response to the number of inhibit cells and the number of fail cells.

6. The semiconductor memory device of claim 1, further comprising a corrected voltage table that stores correction voltage values, wherein the control circuit controls the voltage controller by referencing at least one correction voltage value in the corrected voltage table in response to the number of fail cells.

7. The semiconductor memory device of claim 6, wherein the control circuit stores a number of inhibit cells and controls the voltage controller in response to the number of inhibit cells and the number of fail cells.

8. The semiconductor memory device of claim 7, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the pre-charge voltage in response to the number of fail cells and the number of inhibit cells.

9. The semiconductor memory device of claim 7, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the read voltage in response to the number of fail cells and the number of inhibit cells.

10. The semiconductor memory device of claim 7, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the pre-charge voltage and the read voltage in response to the number of fail cells and the number of inhibit cells.

11. A method of operating a semiconductor memory device comprises:

during a program verification operation, applying a read voltage to a selected word line and applying a pre-charge voltage to a selected bit line, and providing output data in response to the read voltage and pre-charge voltage;

determining a number of fail cells in view of the output data, wherein the number of fail cells is directly related to an increase in voltage on a common source line (CSL) connected to memory cells providing the output data; and

during a subsequent program verification operation, adjusting at least one of the read voltage and the pre-charge voltage in response to the number of fail cells.

12. The method of claim 11, wherein both of the read voltage and the pre-charge voltage are adjusted in response to the number of fail cells.

13. The method of claim 11, wherein the number of fail cells is determined further in view of a number of inhibit cells.

14. The method of claim 13, wherein the number of fail cells is determined with reference to a corrected voltage table storing correction voltage values.

15. A system comprising:

a controller that controls the operation of a semiconductor memory device, wherein the semiconductor memory device comprises;

a memory cell array including a plurality of memory strings, each memory string including memory cells series-connected between a string select transistor and a ground select transistor, wherein the round select transistor is connected to a common source line (CSL);

a plurality of word lines including a selected word line, wherein the selected word line is commonly connected to gates of a row of memory cells extending across the plurality of memory strings;

a plurality of bit lines including a selected bit line, wherein each one of the plurality of bit lines is connected to a corresponding one of the plurality of memory strings;

a page buffer that provides output data from selected memory cells associated with at least one of the selected word line and the selected bit line during a verify read operation;

a fail bit counter that determines a number of fail cells among the selected memory cells;

a voltage controller that generates a read voltage applied to the selected word line during the verify read operation and a pre-charge voltage applied to selected bit line during the read verify operation; and

a control circuit that controls the voltage controller in response to the number of fail cells.

16. The system of claim 15, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the pre-charge voltage in response to the number of fail cells.

17. The system of claim 15, wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the read voltage in response to the number of fail cells.

20. The system of claim 15, further comprising:

a corrected voltage table that stores correction voltage values, wherein the control circuit controls the voltage controller by referencing at least one correction voltage value in the corrected voltage table in response to the number of fail cells.

18. The system of claim wherein the number of fail cells determined by the fail bit counter is defined by a voltage level of on the CSL, and the control circuit corrects the pre-charge voltage and the read voltage in response to the number of fail cells.

19. The system of claim 18, wherein the control circuit stores a number of inhibit cells and controls the voltage controller in response to the number of inhibit cells and the number of fail cells.