Adaptive Frequency Synthesis for a Serial Data Interface

• US 20120155586A1
• Filed: 12/17/2010
• Published: 06/21/2012
• Est. Priority Date: 12/17/2010
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Felder, Matthew, Summers, Mark
• Granted Patent: US 8,605,846 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Claims

1. An integrated interchip sound (I2S) device, comprising

an input port, coupled to receive a bit clock, a left/right clock and input serial data from an I2S interface bus;

a frequency detector, coupled to receive the bit clock and the left/right clock, the frequency detector generates an output frequency control based on a relationship between a first frequency of the left/right clock and a second frequency of the bit clock; and

a clock generator, coupled to receive the output frequency control, the clock generator generates the oversampling clock based on the output frequency control and an oversampling ratio.

2. The integrated interchip sound (I2S) device of claim 1 further comprising:

a shift register, coupled to receive the input serial data, the bit clock and the left/right clock, the shift register converts the input serial data to parallel data; and

a digital-to-analog converter, coupled to receive the parallel data and the oversampling clock, the digital-to-analog converter converts the parallel data to an analog voltage level.

3. The integrated interchip sound (I2S) device of claim 1, wherein the clock generator receives one clock selected from a group consisting of the bit clock and the left/right clock in the I2S interface bus, and the oversampling clock is synchronous with the bit clock, the left/right clock and the input serial data in the I2S interface bus.

4. The integrated interchip sound (I2S) device of claim 1, wherein the frequency detector comprises:

a reference clock generator, generating a reference clock that has a frequency within a range of a known reference frequency;

a first counter, coupled to receive the bit clock and the left/right clock, the first counter generates a first multiple bit output, the bit clock cycles being counted within a left/right clock cycle and the first multiple bit output being the counting result;

a second counter, coupled to receive the left/right clock and the reference clock, the second counter generates a second multiple bit output, the cycles of the higher frequency clock between the left/right clock and the reference clock being counted within the lower frequency clock cycle, the second multiple bit output being the counting result; and

a processing logic, coupled to receive the first and second multiple bit outputs, the processing logic generates the output frequency control.

5. The integrated interchip sound (I2S) device of claim 1, wherein the clock generator is selected from a group consisting of a phase lock loop circuit, a delay lock loop circuit and a frequency lock loop circuit.

6. An integrated interchip sound (I2S) device, comprising

an input port, coupled to receive an input clock and input serial data from an I2S interface bus, the input clock being selected from a group consisting of a left/right clock and a bit clock in the I2S interface bus;

a reference clock generator, generating a reference clock that has a frequency within a range of a known reference frequency;

a frequency detector, coupled to receive the input clock and the reference clock, the frequency detector generates an output frequency control based on a relationship between a first frequency of the input clock and a second frequency of the reference clock;

a first clock generator, coupled to receive the output frequency control, the first clock generator generates the oversampling clock at the third frequency based on the output frequency control and an oversampling ratio; and

a second clock generator, coupled to receive the output frequency control, the second clock generator generates an intermediate clock, the intermediate clock being selected from the group consisting of the bit clock and the left/right clock.

7. The integrated interchip sound (I2S) device of claim 6 further comprising:

a shift register, coupled to receive the input serial data and the input clock, the intermediate clock, the shift register converts the input serial data to parallel data; and

a digital-to-analog converter, coupled to receive the parallel data and the oversampling clock, the digital-to-analog converter converts the parallel data to an analog voltage level.

8. The integrated interchip sound (I2S) device of claim 7, wherein the shift register further comprises a function module, the function module coupled to receive the input clock, the intermediate clock and the input serial data, the function module determines the data boundaries for each channel and synchronizes the input clock, the intermediate clock and the input serial data.

9. The integrated interchip sound (I2S) device of claim 7, wherein the shift register further comprises a function module, the function module coupled to receive the input serial data, the function module determines the bit depth from the input serial data.

10. The integrated interchip sound (I2S) device of claim 6, wherein the first clock generator receives one clock selected from a group consisting of the input clock and the intermediate clock, and the oversampling clock is synchronous with the input clock, the intermediate clock and the input serial data in the I2S interface bus.

11. The integrated interchip sound (I2S) device of claim 6, wherein the second clock generator receives one clock signal selected from a group consisting of the input clock and the oversampling clock, and the intermediate clock is synchronous with the input clock and the input serial data in the I2S interface bus.

12. The integrated interchip sound (I2S) device of claim 6, wherein the frequency detector comprises:

a counter, coupled to receive the input clock and the reference clock, the counter generates a multiple bit output, the cycles of the higher frequency clock between the input clock and the reference clock being counted within the lower frequency clock cycle, the multiple bit output being the counting result; and

a processing logic, coupled to receive the multiple bit output, the processing logic generates the output frequency control.

13. The integrated interchip sound (I2S) device of claim 6, wherein the first clock generator is selected from a group consisting of a phase lock loop circuit, a delay lock loop circuit and a frequency lock loop circuit.

14. A serial data interface device, comprising

an input port, coupled to receive an input clock, an input control and input serial data from a serial interface bus;

a frequency detector, coupled to receive the input clock and the input control, the frequency detector generates an output frequency control based on a relationship between a frequency of the input clock and a second frequency of the input control; and

a clock generator, coupled to receive the output frequency control, the clock generator generates the oversampling clock based on the output frequency control and an oversampling ratio.

15. The serial data interface device of claim 14 further comprising:

a shift register, coupled to receive the input serial data, the input clock and the input control, the shift register converts the input serial data to parallel data; and

a digital-to-analog converter, coupled to receive the parallel data and the oversampling clock, the digital-to-analog converter converts the parallel data to an analog voltage level.

16. The serial data interface device of claim 14, wherein the clock generator is coupled to receive one signal selected from a group consisting of the input clock and the input control, and the oversampling clock is synchronous with the input signal, the input control and the input serial data in the serial data interface.

17. The serial data interface device of claim 14, wherein the frequency detector comprises:

a reference clock generator, generating a reference clock that has a frequency within a range of a known reference frequency;

a counter, coupled to receive the input clock and the reference clock, the counter generates a multiple bit output, the cycles of the higher frequency clock between the input clock and the reference clock being counted within the lower frequency clock cycle, the multiple bit output being the counting result; and

a processing logic, coupled to receive the multiple bit output, the processing logic generates the output frequency control.

18. The serial data interface device of claim 14, wherein the clock generator is selected from a group consisting of a phase lock loop circuit, a delay lock loop circuit and a frequency lock loop circuit.

19. A method of generating an oversampling clock in a serial data interface device, the method comprise the steps of:

receiving an input control, an input clock and input serial data from a serial data interface;

generating a reference clock which has a frequency within a certain range of a known frequency;

comparing a first frequency of the reference clock to a second frequency of one signal selected from a group of the input clock and input control to identify an output frequency control based on a relationship between the first frequency and the second frequency; and

generating the oversampling clock based on the output frequency control.

20. The method of claim 19, where comparing the first frequency of the reference clock to the second frequency of one signal selected from a group of the input clock and input control to identify the output frequency control based on the relationship between the first frequency and the second frequency comprises the steps of:

counting the higher frequency clock cycles of the reference clock and the input clock within the lower frequency clock cycles to generate a multiple bit signal;

comparing the multiple bit signal with available options identified by the relationship between the first frequency and the second frequency; and

identifying the output frequency control.