SEMICONDUCTOR SENSOR RELIABILITY

• US 20120158392A1
• Filed: 12/15/2010
• Published: 06/21/2012
• Est. Priority Date: 12/15/2010
• Status: Active Grant

• Current Assignee: SDEP Corporation
• Original Assignee: IP Cube Partners Company Limited
• Inventors: Kim, Moon J.
• Granted Patent: US 8,935,143 B2
• Time in Patent Office: Days
• US Class Current: 703/13
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G06F 2119/04 Ageing analysis or optimisation against ageing
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.

Claims

1. A semiconductor sensor reliability system, comprising:

a semiconductor system comprising a plurality of functional blocks; and

a plurality of sensors positioned on the plurality of functional blocks, wherein each of the plurality of functional blocks has at least one sensor, and wherein each of the plurality of sensors models a behavior of the location in which it is positioned.

2. The semiconductor sensor reliability system of claim 1, wherein the at least one sensor is positioned at a location within the functional block subject to semiconductor system manufacturing process variation.

3. The semiconductor sensor reliability system of claim 1, wherein at least one of the plurality of sensors is positioned at a connection point between functional blocks.

4. The semiconductor sensor reliability system of claim 1, each of the plurality of sensors having a mode selection input for selecting a mode of the plurality of sensors and an operational trigger input for enabling the plurality of sensors to model the behavior.

5. The semiconductor sensor reliability system of claim 4, the mode selection input enabling the plurality of sensors to have:

an operational mode in which the plurality of sensors are subject to an aging process; and

a measurement mode in which an age of the plurality of sensors are outputted.

6. The semiconductor sensor reliability system of claim 1, each of the plurality of sensors comprising a plurality of sensor stages connected as a network and a self digitizer.

7. The semiconductor sensor reliability system of claim 6, each of the plurality of sensor stages comprising a plurality of devices being selected from a group consisting of:

aging-resistant devices and aging-sensitive devices.

8. A semiconductor sensor reliability system, comprising:

a semiconductor system comprising a plurality of functional blocks; and

a plurality of sensors positioned on the plurality of functional blocks, wherein each of the plurality of functional blocks has at least one sensor, and wherein each of the plurality of sensors models an aging process of the location in which it is positioned.

9. The semiconductor sensor reliability system of claim 8, wherein the at least one sensor is positioned at a location within the functional block subject to semiconductor system manufacturing process variation.

10. The semiconductor sensor reliability system of claim 8, wherein at least one of the plurality of sensors is positioned at a connection point between functional blocks.

11. The semiconductor sensor reliability system of claim 8, each of the plurality of sensors having a mode selection input for selecting a mode of the plurality of sensors and an operational trigger input for enabling the plurality of sensors to model the aging process.

12. The semiconductor sensor reliability system of claim 11, the mode selection input enabling the plurality of sensors to have:

an operational mode in which the plurality of sensors are subject to the aging process; and

a measurement mode in which an age of the plurality of sensors are outputted.

13. The semiconductor sensor reliability system of claim 8, each of the plurality of sensors comprising a plurality of sensor stages connected as a network and a self digitizer.

14. The semiconductor sensor reliability system of claim 13, each of the plurality of sensor stages comprising a plurality of devices being selected from a group consisting of:

aging-resistant devices and aging-sensitive devices.

15. A method for sensing semiconductor reliability, comprising:

positioning a plurality of sensors on a plurality of functional blocks to observe defect-sensitive locations within a semiconductor system, wherein each of the plurality of functional blocks has at least one sensor; and

engaging an operational model of the plurality of the sensors to cause each sensor to model an aging process of the defect-sensitive location in which it is positioned.

16. The method of claim 15, wherein the defect-sensitive location comprises at least one of the following:

a location within the functional block subject to semiconductor system manufacturing process variation, and a connection point between functional blocks.

17. The method of claim 15, further comprising receiving output from the plurality of sensors, the output comprising a sensor age of each of the plurality of sensors due to the aging process.

18. The method of claim 15, each sensor comprising a plurality of sensor stages connected as a network and a self digitizer, each of the plurality of stages having multiple inputs and multiple outputs.

19. The method of claim 18, each of the plurality of stages comprising a plurality of devices coupled in a Complimentary Metal-Oxide Semiconductor (CMOS)-like fashion.

20. The method of claim 19, the plurality of devices being selected from a group consisting of:

aging-resistant devices and aging-sensitive devices.