METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CACHE SIZING AND CACHE OPERATING VOLTAGE MANAGEMENT FOR OPTIMAL POWER PERFORMANCE
First Claim
1. A method comprising:
- monitoring a last level cache (LLC) to identify a reduced amount of the cache being used by a processor to process data;
reducing an amount of cache available for use by the processor, based on the reduced amount of cache being used;
reducing an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used.
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Accused Products
Abstract
Embodiments of the invention relate to increased energy efficiency and conservation by reducing and increasing an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.
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Citations
20 Claims
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1. A method comprising:
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monitoring a last level cache (LLC) to identify a reduced amount of the cache being used by a processor to process data; reducing an amount of cache available for use by the processor, based on the reduced amount of cache being used; reducing an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus comprising:
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a processor having an execution unit including a first core and a second core that share a last level cache (LLC); the processor execution unit coupled to a power control unit and to a FSM, the FSM coupled to the power control unit; monitor code of the power control unit configured to monitor the cache to identify a reduced amount of cache being used by the processor to process data; the FSM configured to reduce the amount of cache available for use by the processor, based on a cache size control signal received from the power control unit, the cache size control signal based on the reduced amount of cache being used; the power control unit configured to reduce an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a computing device having a processor and memory;
the processor coupled to the memory to process data stored in the memory;the processor having an execution unit including a first core and a second core that share a last level cache (LLC); the processor execution unit coupled to a power control unit and to a FSM, the FSM coupled to the power control unit; monitor code of the power control unit configured to monitor the cache to identify a reduced amount of cache being used by the processor to process data; the FSM configured to reduce the amount of cache available for use by the processor, based on a cache size control signal received from the power control unit, the cache size control signal based on the reduced amount of cache being used; the power control unit configured to reduce an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used. - View Dependent Claims (18, 19, 20)
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Specification