METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CACHE SIZING AND CACHE OPERATING VOLTAGE MANAGEMENT FOR OPTIMAL POWER PERFORMANCE

• US 20120159074A1
• Filed: 12/23/2011
• Published: 06/21/2012
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intel Corporation
• Inventors: Sodhi, Inder M., Damaraju, Satish K., Jahagirdar, Sanjeev S., Wells, Ryan D.
• Granted Patent: US 8,713,256 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the invention relate to increased energy efficiency and conservation by reducing and increasing an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.

Claims

1. A method comprising:

monitoring a last level cache (LLC) to identify a reduced amount of the cache being used by a processor to process data;

reducing an amount of cache available for use by the processor, based on the reduced amount of cache being used;

reducing an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used.

2. The method of claim 1, further comprising:

after reducing the amount of cache available and reducing the amount of power supplied to the cache, monitoring the cache to identify an increased amount of cache being used by the processor to process data and to identify smart cache expand heurestis;

increasing an amount of cache available for use by the processor, based on the increased amount of cache being used;

increasing an amount of power supplied to the cache and to the processor, based on the increased amount of cache being used.

3. The method of claim 2, wherein the reduced amount and the increased amount of the cache being used are related to an operating system and an application running on the processor;

and wherein the reduced amount and the increased amount of the cache available for use by the processor are based on metrics, heuristics or factors calculated based on an amount of cache being used.

4. The method of claim 2, wherein the reduced amount and the increased amount of power supplied to the cache and to the processor is based on the reduced amount and the increased amount of cache available for use by the processor.

5. The method of claim 2, wherein reducing the amount of cache available comprises removing the processors ability to access a portion of the cache, based on the reduced amount of cache being used;

and wherein reducing the amount of power supplied to the cache comprises removing power from a part of the cache having a size less than the size of the portion of the cache.

6. The method of claim 5, monitoring the cache to identify the reduced amount and the increased amount of the cache being used comprises periodically “

sniffing”

the cache; and

wherein the portion of the cache is selected to be in half MegaByte increments.

7. The method of claim 1, further comprising, prior to monitoring, the processor processing data comprising the data is stored in the cache.

8. The method of claim 1, further comprising:

using a first power supply to increase and decrease the amount of power and a frequency supplied to the cache and to the processor; and

using a second power supply to supply a fixed amount of power and frequency to a Bus Interface Unit of the processor.

9. An apparatus comprising:

a processor having an execution unit including a first core and a second core that share a last level cache (LLC);

the processor execution unit coupled to a power control unit and to a FSM, the FSM coupled to the power control unit;

monitor code of the power control unit configured to monitor the cache to identify a reduced amount of cache being used by the processor to process data;

the FSM configured to reduce the amount of cache available for use by the processor, based on a cache size control signal received from the power control unit, the cache size control signal based on the reduced amount of cache being used;

the power control unit configured to reduce an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used.

10. The apparatus of claim 9, further comprising:

the monitor code configured to, after reducing the amount of cache available and reducing the amount of power supplied to the cache, monitor the cache to identify an increased amount of cache being used by the processor to process data and to identify smart cache expand heurestis;

the FSM configured to increase an amount of cache available for use by the processor, based on the increased amount of cache being used;

the PCU configured to increase an amount of power supplied to the cache and to the processor, based on the increased amount of cache being used.

11. The apparatus of claim 10 further comprising:

the PCU configured to reduced an amount and increased an amount of power supplied to the cache and to the processor, based on the reduced amount and the increased amount of cache available for use by the processor.

12. The apparatus of claim 10 further comprising:

an operating system and an application running on the processor and causing the reduced amount and the increased amount of the cache being; and

wherein the reduced amount and the increased amount of the cache available for use by the processor are based on metrics, heuristics or factors calculated based on an amount of cache being used.

13. The apparatus of claim 12 further comprising:

the monitor code configured to periodically “

sniffing”

the cache to identify the reduced amount and the increased amount of the cache being used, wherein the portion of the cache is selected to be in half MegaByte increments.

14. The apparatus of claim 9 further comprising:

the FSM configured to remove the processors ability to access a portion of the cache, based on the reduced amount of cache being used; and

the power control unit configured to remove power from a part of the cache having a size less than the size of the portion of the cache.

15. The apparatus of claim 9 further comprising:

the processor processing data comprising the data is stored in the cache, prior to monitoring.

16. The apparatus of claim 9 further comprising:

the processor further comprising a Bus Interface Unit;

wherein the power control unit uses a first power supply to increase and decrease the amount of power and a frequency supplied to the cache and to the processor, and uses a second power supply to supply a fixed amount of power and frequency to the Bus Interface Unit.

17. A system comprising:

a computing device having a processor and memory;

the processor coupled to the memory to process data stored in the memory;

the processor having an execution unit including a first core and a second core that share a last level cache (LLC);

the processor execution unit coupled to a power control unit and to a FSM, the FSM coupled to the power control unit;

monitor code of the power control unit configured to monitor the cache to identify a reduced amount of cache being used by the processor to process data;

the FSM configured to reduce the amount of cache available for use by the processor, based on a cache size control signal received from the power control unit, the cache size control signal based on the reduced amount of cache being used;

the power control unit configured to reduce an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used.

18. The system of claim 17, further comprising:

the monitor code configured to, after reducing the amount of cache available and reducing the amount of power supplied to the cache, monitor the cache to identify an increased amount of cache being used by the processor to process data and to identify smart cache expand heurestis;

the FSM configured to increase an amount of cache available for use by the processor, based on the increased amount of cache being used;

the PCU configured to increase an amount of power supplied to the cache and to the processor, based on the increased amount of cache being used.

19. The system of claim 18, further comprising:

the PCU configured to reduced an amount and increased an amount of power supplied to the cache and to the processor, based on the reduced amount and the increased amount of cache available for use by the processor; and

wherein the reduced amount and the increased amount of the cache available for use by the processor are based on metrics, heuristics or factors calculated based on an amount of cache being used.

20. The system of claim 17, further comprising:

the FSM configured to remove the processors ability to access a portion of the cache, based on the reduced amount of cache being used; and

the power control unit configured to remove power from a part of the cache having a size less than the size of the portion of the cache.