Integrated device

• US 20120159089A1
• Filed: 02/16/2012
• Published: 06/21/2012
• Est. Priority Date: 09/07/2005
• Status: Active Grant

• Current Assignee: Motofumi Kashiwaya
• Original Assignee: Motofumi Kashiwaya
• Inventors: Kashiwaya, Motofumi
• Granted Patent: US 9,400,762 B2
• Time in Patent Office: Days
• US Class Current: 711/149
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Claims

1-32. -32. (canceled)

33. An integrated device comprising:

a memory system including a plurality of unit memories able to be independently accessed;

at least one processing module able to access the plurality of unit memories;

interconnects of a basic route shared by the plurality of unit memories for selectively accessing to one arbitrary unit memory of the plurality of unit memories by the processing module; and

interconnects of a bypass route for accessing to at least one predetermined unit memory of the plurality of unit memories by the processing module.

34. An integrated device as set forth in claim 33, wherein the bypass route is utilized when shorter than a route length through the basic route.

35. An integrated device as set forth in claim 33, including:

a planar configuration formed by a memory layer at which the plurality of unit memories are arranged; and

an interconnect layer including interconnects in a stacking direction connecting the memory layer and either the basic route, the bypass route, or combination thereof.

36. An integrated device as set forth in claim 33, including:

a planar configuration formed by

a processing module layer in which the processing module is arranged; and

an interconnect layer including interconnects in a stacking direction connecting the processing module layer and either the basic route, the bypass route, or combination thereof.

37. An integrated device as set forth in claim 35, wherein the interconnects of the bypass route include interconnects in the stacking direction connected to the middle of the basic route.

38. An integrated device as set forth in claim 35, wherein the interconnect layer includes interconnects of a planar direction forming part of either the basic route, the bypass route, or combination thereof.

39. An integrated device as set forth in claim 38, wherein the interconnects of a planar direction form part of interconnects of a matrix shape formed in the interconnect layer.

40. An integrated device as set forth in claim 33, including:

a plurality of planar configurations arranged in parallel; and

interconnects of a normal direction connecting the plurality of planar configurations;

wherein the plurality of planar configurations includes

a processing module planar configuration in which the processing module is arranged; and

a memory planar configuration in which the plurality of unit memories are arranged; and

the interconnects of a normal direction includes interconnects forming part of the basic route and the bypass route.

41. An integrated device as set forth in claim 33, including

a plurality of processing modules;

wherein which access route of the basic route and the bypass route is used is determined based on a relative position between the accessing processing module and the unit memory to be accessed.