Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure

• US 20120159118A1
• Filed: 12/16/2010
• Published: 06/21/2012
• Est. Priority Date: 12/16/2010
• Status: Abandoned Application

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Inventors: Loh, Wei Keat, Ong, Kang Eu, Wong, Au Seong, Wong, Shaw Fong
• Application Number:
  US12/970,114
• Publication Number:
  US 20120159118A1
• Time in Patent Office: Days
• US Class Current: 712/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

Claims

1. A lower integrated circuit (IC) package, the lower IC package for coupling with an upper IC package to form a package-on-package assembly, the lower IC package comprising:

a substrate having a first side and an opposing second side;

an IC die coupled with the first side of the substrate;

an encapsulant, the encapsulant disposed over at least a portion of a surface of the die and over at least a portion of the first side of the substrate;

an interposer having a first side and an opposing second side, the second side of the interposer facing the first side of the substrate;

a number of interconnects electrically coupling the interposer with the substrate; and

a plurality of terminals disposed on the first side of the interposer, the plurality of terminals for forming electrical connections with the upper IC package.

2. The lower IC package of claim 1, further comprising a barrier to control flow of the encapsulant.

3. The lower IC package of claim 2, wherein the barrier inhibits flow of the encapsulant toward the number of interconnects.

4. The lower IC package of claim 2, wherein the bather comprises a structure selected from a group consisting of a dam, a coating that is non-wetting with respect to the encapsulant, and a trench.

5. The lower IC package of claim 1, wherein a portion of the surface of the IC die is substantially free of encapsulant.

6. The lower IC package of claim 1, wherein the encapsulant extends over at least a portion of a surface of one or more of the number of interconnects.

7. The lower IC package of claim 6, wherein the encapsulant substantially surrounds all of the interconnects.

8. The lower IC package of claim 1, wherein the interposer comprises a frame having an opening.

9. The lower IC package of claim 8, wherein the encapsulant extend into the opening.

10. The lower IC package of claim 9, wherein the encapsulant extends above the first side of the interposer.

11. The lower IC package of claim 1, further comprising an underfill material disposed between the IC die and the first side of the substrate, wherein the encapsulant contacts at least a portion of the underfill material.

12. The lower IC package of claim 1, further comprising a number of wirebonds electrically coupling the IC die with the substrate, wherein the encapsulant is disposed over at least one of the wirebonds.

13. The lower IC package of claim 1, wherein the substrate is built up directly over the IC die.

14. The lower IC package of claim 1, wherein at least one of the plurality of terminals comprises an electrically conductive pad, the pad capable of forming an electrical connection with a metal bump extending from the upper IC package.

15. The lower IC package of claim 1, further comprising a second plurality of terminals disposed on the second side of the substrate, the second plurality of terminal for electrically coupling the lower IC package with a circuit board.

16. The lower IC package of claim 1, further comprising at least one other IC die stacked over the IC die, wherein the encapsulant is disposed over at least a portion of a surface of the at least one other IC die.

17. A package-on-package (PoP) assembly comprising:

a lower integrated circuit (IC) package, the lower IC package including a substrate having a first side and an opposing second side, an IC die coupled with the first side of the substrate, an interposer having a first side and an opposing second side that faces the first side of the substrate, a number of interconnects electrically coupling the interposer with the substrate, and an encapsulant, the encapsulant disposed over at least a portion of a surface of the die and over at least a portion of the first side of the substrate;

an upper IC package; and

a plurality of interconnects electrically coupling the upper IC package with the first side of the interposer.

18. The PoP assembly of claim 17, wherein the upper IC package comprises at least one IC die disposed on a second substrate.

19. The PoP assembly of claim 18, further comprising:

an electrically conductive pad disposed on the first side of the interposer;

wherein at least one of the plurality of interconnects includes a solder bump extending from the second substrate and coupled with the conductive pad.

20. The PoP assembly of claim 17, further comprising a barrier disposed in the lower IC package to control flow of the encapsulant.

21. The PoP assembly of claim 20, wherein the barrier inhibits flow of the encapsulant toward the number of interconnects.

22. The PoP assembly of claim 20, wherein the barrier comprises a structure selected from a group consisting of a dam, a coating that is non-wetting with respect to the encapsulant, and a trench.

23. The PoP assembly of claim 17, wherein the encapsulant extends over at least a portion of a surface of one or more of the number of interconnects.

24. The PoP assembly of claim 23, wherein the encapsulant substantially surrounds all of the number of interconnects.

25. The PoP assembly of claim 17, wherein the interposer comprises a frame having an opening.

26. The PoP assembly of claim 25, wherein the encapsulant extend into the opening.

27. The PoP assembly of claim 26, wherein the encapsulant extends above the first side of the interposer.

28. The PoP assembly of claim 17, wherein the substrate of the lower IC package is built up directly over the IC die.

29. The PoP assembly of claim 17, further comprising a plurality of terminals on the second side of the substrate of the lower IC package, the plurality of terminals for electrically coupling the PoP assembly with a circuit board.

30. The PoP assembly of claim 17, further comprising at least one other IC die stacked over the IC die of the lower IC package, wherein the encapsulant is disposed over at least a portion of a surface of the at least one other IC die.

31. A computing system comprising:

a mainboard;

a package-on-package (PoP) assembly disposed on the mainboard, the PoP assembly including a lower IC package, an upper IC package, and a plurality of interconnects electrically coupling the upper IC package with the lower IC package;

a processing system disposed in the PoP assembly; and

at least one user interface device disposed on the mainboard;

wherein the lower IC package comprises a substrate having a first side and an opposing second side, an IC die coupled with the first side of the substrate, an interposer having a first side and an opposing second side that faces the first side of the substrate, a number of interconnects electrically coupling the interposer with the substrate, and an encapsulant, the encapsulant disposed over at least a portion of a surface of the die and over at least a portion of the first side of the substrate; and

wherein the plurality of interconnects extend between the first side of the interposer and the upper IC package.

32. The computing system of claim 31, wherein the IC die of the lower IC package includes the processing system.

33. The computing system of claim 32, further comprising a memory disposed in the upper IC package of the PoP assembly.

34. The computing system of claim 31, wherein the PoP assembly includes at least part of a communications system.

35. The computing system of claim 31, wherein the user interface device comprises a device selected from a group consisting of an audio input device, an audio output device, a keypad, a touch screen, and a graphics display.

36. The computing system of claim 31, further comprising at least one component selected from a group consisting of an antenna, a power supply, an IC device, a voltage regulator, a radiation shield, a cooling device, and a passive electrical device.