Performing Variation-Aware Profiling And Dynamic Core Allocation For A Many-Core Processor

• US 20120159496A1
• Filed: 12/20/2010
• Published: 06/21/2012
• Est. Priority Date: 12/20/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vangal, Sriram R., Borkar, Nitin Y., De, Vivek K., Dighe, Saurabh
• Granted Patent: US 9,063,730 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core; and

a scheduler coupled to receive the frequency profiles and the leakage power profiles of the plurality of cores and to schedule an application on at least some of the plurality of cores based at least in part on the frequency profiles and the leakage power profiles.

2. The processor of claim 1, wherein the scheduler is to schedule the application further based on application parameters, a performance requirement of the application, and power management information of the processor.

3. The processor of claim 2, wherein the scheduler is to schedule the application at a minimum energy point that meets the performance requirement of the application, the performance requirement including an execution time target.

4. The processor of claim 2, wherein the application parameters include a operations per second target, a number of data units transferred, a compute activity factor, and a communication-computation overlap factor.

5. The processor of claim 2, wherein the application parameters include inputs from an energy monitor, wherein the energy monitor is to extract a dynamic switching capacitance of a compute block and provide voltage and frequency pairs for an optimum minimal energy operational point.

6. The processor of claim 1, wherein the processor comprises a multi-core processor including a memory to store the frequency profiles and the leakage power profiles of the plurality of cores.

7. The processor of claim 6, wherein the scheduler is to schedule the application to a first set of cores based on a within-die variation between the leakage power profiles and the frequency profiles of the plurality of cores.

8. The processor of claim 7, wherein the multi-core processor is to operate at a single frequency and multiple voltages, and wherein the scheduler is to independently control a voltage provided to each of the first set of cores.

9. The processor of claim 7, wherein the multi-core processor is to operate at a single voltage and the scheduler is to adjust a frequency of each of the plurality of cores independently.

10. The processor of claim 7, wherein the multi-core processor is to operate at a plurality of voltages and frequencies and the scheduler is to adjust a voltage and frequency of each of the plurality of cores independently.

11. The processor of claim 7, wherein the scheduler is to map an application to the first set of cores having a higher maximum frequency than a second set of cores, and to clock gate each of the first set of cores at a conclusion of a workload scheduled to the corresponding core.

12. The processor of claim 1, wherein the scheduler is to enable a first plurality of cores having a higher maximum frequency and to disable a second plurality of cores having a lower maximum frequency.

13. The processor of claim 12, wherein the scheduler is to enable the first plurality of cores in a first voltage domain and disable the second plurality of cores in a second voltage domain, when the first voltage domain has a lower leakage profile than the second voltage domain.

14. The processor of claim 1, wherein the processor further includes a plurality of thermal sensors and the scheduler is to schedule the application further based on temperature information from the plurality of thermal sensors.

15. A method comprising:

receiving profile information from a plurality of cores of a many-core processor, the profile information including a frequency profile and a leakage power profile of each of the plurality of cores;

determining an optimal operating point for execution of an application on the many-core processor based at least in part on the profile information and application parameters of the application, wherein a subset of cores of the many-core processor are active at the optimal operating point; and

enabling the subset of cores and disabling remaining cores of the many-core processor.

16. The method of claim 15, wherein determining the optimal operating point includes selecting an independent voltage to be provided to each of the subset of cores, wherein the many-core processor is to operate at a single frequency and multiple voltages.

17. The method of claim 15, wherein determining the optimal operating point includes selecting an independent frequency at which each of the subset of cores is to operate, wherein the many-core processor is to operate at a single voltage and multiple frequencies.

18. The method of claim 17, wherein the subset of cores have a higher maximum frequency than the remaining cores, and further comprising clock gating each of the subset of cores at a conclusion of a workload scheduled to the corresponding core.

19. A system comprising:

a many-core processor including a plurality of cores and a memory to store frequency profiles and leakage power profiles for the plurality of cores, wherein the many-core processor is to schedule an application to a selected number of the plurality of cores based on within-die variations in the frequency profiles and the leakage power profiles; and

a dynamic random access memory (DRAM) coupled to the many-core processor.

20. The system of claim 19, wherein the selected number of the plurality of cores have a higher frequency profile than non-selected cores.

21. The system of claim 20, wherein the many-core processor is to clock gate the non-selected cores.

22. The system of claim 19, further comprising a scheduler coupled to receive the frequency profiles and the leakage power profiles of the plurality of cores and to schedule the application further based on application parameters, a performance requirement of the application, and power management information of the many-core processor, at a minimum energy point that meets the performance requirement, the performance requirement including an execution time target.