SUBSTRATE, MANUFACTURING METHOD OF SUBSTRATE, SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT

• US 20120161098A1
• Filed: 08/20/2009
• Published: 06/28/2012
• Est. Priority Date: 08/20/2009
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hiura, Hidefumi, Tsukagoshi, Kazuhito
• Application Number:
  US13/391,104
• Publication Number:
  US 20120161098A1
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: C01B 2204/04 Specific amount of layers or specific thickness
• CPC Class Codes: C01B 32/186 by chemical vapour deposition [CVD]
• CPC Class Codes: C23C 16/0218 in a reactive atmosphere C23C16/0227 takes precedence
• CPC Class Codes: C23C 16/0281 of metallic sub-layers C23C16/029 takes precedence
• CPC Class Codes: C23C 16/26 Deposition of carbon only
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A semiconductor device is provided which is produced from a high-quality and large-area graphene substrate and is capable of fully exhibiting superior electronic properties that graphene inherently has. The semiconductor device is capable of realizing increased operation speed, reduced power consumption, and higher degree of integration, and thus is capable of improving the reliability and productivity. Electrical short circuit between a graphene layer (4) and a metal catalyst layer for growth of graphene is prevented by causing the metal catalyst layer to be absorbed as a compound/alloyed layer 5 at the interface between a substrate (1) and an oxide layer (2).

Claims

1. A substrate formed by stacking, on a semiconductor or metal layer, a graphene layer formed by chemical vapor deposition using a metal catalyst, an oxide layer for diffusing the metal catalyst, and a compound or alloyed layer formed by combination or alloying between the metal catalyst and the semiconductor or metal layer, wherein the substrate, the compound or alloyed layer, the oxide layer, and the graphene layer is stacked in this order.

4. The substrate as claimed in claim 1, wherein the metal catalyst is at least one selected from the group consisting of chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

5. The substrate as claimed in claim 1, claim 1, wherein the oxide layer is formed of at least one selected from the group consisting of lithium oxide (I)/Li₂O, beryllium oxide (II)/BeO, boron oxide (II)/B₂O₃, sodium oxide (I)/Na₂O, magnesium oxide (II)/MgO, aluminum oxide (III)/Al₂O₃, silicon oxide (IV)/SiO₂, phosphorus oxide (V)/P₄O₁₀, phosphorus oxide (IV)/PO₂, potassium oxide (I)/K₂O, calcium oxide (II)/CaO, scandium oxide (III)/Sc₂O₃, titanium oxide (IV)TiO₂, titanium oxide (III, IV)/Ti₃O₅, titanium oxide (III)/Ti₂O₃, titanium oxide (II)/TiO, vanadium oxide (V)N₂O₅, vanadium oxide (IV)/VO₂, vanadium oxide (III)/V₂O₃, vanadium oxide (II)/VO, chromium oxide (II)/CrO, chromium oxide (II,III)/Cr₃O₄, chromium oxide (III)/Cr₂O₃, manganese oxide (IV)/MnO₂, manganese oxide (III)/Mn₂O₃, manganese oxide (II,III)/Mn₃O₄, manganese oxide (II)/MnO, iron oxide (III)/Fe₂O₃, iron oxide (II)/FeO, iron oxide (II,III)/Fe₃O₄, cobalt oxide (II,III)/Co₃O₄, cobalt oxide (II)/CoO, nickel oxide (II)/NiO, copper oxide (II)/CuO, copper oxide (I)/Cu₂O, zinc oxide (II)/ZnO, gallium oxide (III)/Ga₂O₃, germanium oxide (IV)/GeO₂, arsenic oxide(III)/As₂O₃, selenium oxide (IV)/SeO₂, rubidium oxide (IV)/RuO₂, strontium oxide (II)/SrO, yttrium oxide (III)/Y₂O₃, zirconium oxide (IV)/ZrO₂, niobium oxide (V)/Nb₂O₅, niobium oxide (IV)/NbO₂, niobium oxide (II)/NbO, molybdenum oxide (VI)/MoO₃, molybdenum oxide (IV)/MoO₂, ruthenium oxide (VI)/RuO₃, ruthenium oxide (VIII)/RuO₄, ruthenium oxide (IV)/RuO₂, rhodium oxide (III)/Rh₂O₃, palladium oxide (II)/PdO, silver oxide (I)/Ag₂O, cadmium oxide (II)/CdO, indium oxide (III)/In₂O₃, tin oxide (IV)/SnO₂, antimony oxide (III)/Sb₂O₃, tellurium oxide (IV)/TeO₂, barium oxide (II)/BaO, cerium oxide (IV)/CeO₂, cerium oxide (III)/Ce₂O₃, praseodymium oxide (III)/Pr₂O₃, neodymium oxide (III)/Nd₂O₃, samarium oxide (III)/Sm₂O₃, europium oxide (III)/Eu₂O₃, gadolinium oxide (III)/Gd₂O₃, terbium oxide (III)/Tb₂O₃, dysprosium oxide (III)/Dy₂O₃, hafnium oxide (IV)/HfO₂, tantalum oxide (V)/Ta₂O₅, tungsten oxide (VI)/WO₃, tungsten oxide (IV)/WO₂, rhenium oxide (IV)/ReO₂, osmium oxide (IV)/OsO₂, iridium oxide (IV)/IrO₂, mercury oxide (I)/Hg₂O, lead oxide (IV)/PbO₂, lead oxide (II,III)/Pb₃O₄, lead oxide (II)/PbO, bismuth oxide (III)/Bi₂O₃, thorium oxide(IV)/ThO₂, and uranium oxide (IV)/UO₂.

6. The substrate as claimed in claim 1, wherein the semiconductor or metal layer is formed of at least one selected from the group consisting of boron (B), aluminum (Al), silicon (Si), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), germanium (Ge), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), bismuth (Bi), gallium arsenide (GaAs), indium phophide (InP), indium antimonide (InSb), GaN (gallium nitride), AlN (aluminum nitride), and silicon carbide (SiC).

7. A semiconductor element manufactured with the substrate as claimed in claim 1.

2. A substrate formed by stacking, on a semiconductor or metal layer, an atomic layer thin film formed by reducing an oxide layer with a graphene layer formed by chemical vapor deposition using a metal catalyst, the oxide layer for diffusing the metal catalyst, and a compound or alloyed layer formed by combination or alloying between the metal catalyst and the semiconductor or metal layer, wherein the substrate, the compound or alloyed layer, the oxide layer, and the atomic layer thin film is stacked in this order.

3. A substrate formed by stacking, on a semiconductor or metal layer, a graphene layer formed by chemical vapor deposition using a metal catalyst, an atomic layer thin film formed by reducing an oxide layer with the graphene layer, the oxide layer for diffusing the metal catalyst, and a compound or alloyed layer formed by combination or alloying between the metal catalyst and the semiconductor or metal layer, wherein the substrate, the compound or alloyed layer, the oxide layer, the atomic layer thin film, and the graphene layer is stacked in this order.

8-19. -19. (canceled)