SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20120161126A1
• Filed: 12/20/2011
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 8,883,556 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device capable of high speed operation is provided. Further, a semiconductor device in which change in electric characteristics due to a short channel effect is hardly caused is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed by self-aligned process in which one or more elements selected from Group 15 elements are added to the semiconductor layer with the use of a gate electrode as a mask. The source region and the drain region can have a wurtzite crystal structure.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer having crystallinity;

a gate insulating layer; and

a gate electrode,

wherein the oxide semiconductor layer comprises a first oxide semiconductor region and a pair of second oxide semiconductor regions, wherein the first oxide semiconductor region is sandwiched between the pair of second oxide semiconductor regions,

wherein the first oxide semiconductor region overlaps with the gate electrode with the gate insulating layer interposed therebetween, and

wherein each of the pair of second oxide semiconductor regions comprises at least one element selected from Group 15 elements.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises zinc, indium, or gallium

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a non-single-crystal semiconductor.

4. The semiconductor device according to claim 1, wherein a concentration of the element included in the pair of second oxide semiconductor regions is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

5. The semiconductor device according to claim 1, wherein the pair of second oxide semiconductor regions has a wurtzite crystal structure.

6. The semiconductor device according to claim 1, wherein the element included in the pair of second oxide semiconductor regions is nitrogen.

7. A semiconductor device comprising:

an oxide semiconductor layer having crystallinity;

a gate insulating layer; and

a gate electrode,

wherein the oxide semiconductor layer comprises a first oxide semiconductor region, a pair of second oxide semiconductor regions, and a pair of third oxide semiconductor regions,

wherein the first oxide semiconductor region is sandwiched between the pair of third oxide semiconductor regions,

wherein the pair of third oxide semiconductor regions is sandwiched between the pair of second oxide semiconductor regions,

wherein the first oxide semiconductor region overlaps with the gate electrode with the gate insulating layer interposed therebetween, and

wherein each of the pair of second oxide semiconductor regions and the pair of third oxide semiconductor regions comprises at least one element selected from Group 15 elements.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises zinc, indium, or gallium

9. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises a non-single-crystal semiconductor.

10. The semiconductor device according to claim 7, wherein a concentration of the element included in the pair of second oxide semiconductor regions is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

11. The semiconductor device according to claim 7, wherein the pair of second oxide semiconductor regions and the pair of third oxide semiconductor regions have a wurtzite crystal structure.

12. The semiconductor device according to claim 7, wherein the element included in the pair of second oxide semiconductor regions and the pair of third oxide semiconductor regions is nitrogen.

13. The semiconductor device according to claim 7, wherein a concentration of the element included in the pair of third oxide semiconductor regions is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

14. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer having crystallinity;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode over the gate insulating layer; and

adding at least one element selected from Group 15 elements to a region of the oxide semiconductor layer with the use of the gate electrode as a mask,

wherein the region of the oxide semiconductor layer to which the element is added obtains a wurtzite crystal structure by heat treatment.

15. The method for manufacturing a semiconductor device, according to claim 14, wherein the oxide semiconductor layer comprises zinc, indium, or gallium.

16. The method for manufacturing a semiconductor device, according to claim 14, wherein the oxide semiconductor layer comprises a non-single-crystal semiconductor.

17. The method for manufacturing a semiconductor device, according to claim 14, wherein the element is nitrogen.

18. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer having crystallinity;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode over the gate insulating layer;

adding at least one element selected from Group 15 elements to a first region of the oxide semiconductor layer with the use of the gate electrode as a mask in a first addition step;

forming a sidewall on a side surface of the gate electrode; and

adding at least one element selected from Group 15 elements to a second region of the oxide semiconductor layer with the use of the gate electrode and the sidewall as masks in a second addition step; and

heating the oxide semiconductor layer thereby forming a wurtzite crystal structure in the first region and the second region of the oxide semiconductor layer.

19. The method for manufacturing a semiconductor device, according to claim 18, wherein the oxide semiconductor layer comprises zinc, indium, or gallium.

20. The method for manufacturing a semiconductor device, according to claim 18, wherein the oxide semiconductor layer comprises a non-single-crystal semiconductor.

21. The method for manufacturing a semiconductor device, according to claim 18, wherein the element is nitrogen.

22. The method for manufacturing a semiconductor device, according to claim 18, wherein the element added to the first region of the oxide semiconductor layer in the first addition step is nitrogen.

23. The method for manufacturing a semiconductor device, according to claim 18, wherein the element added to the second region of the oxide semiconductor layer in the second addition step is nitrogen.

24. The method for manufacturing a semiconductor device, according to claim 18, wherein a concentration of the element added to the first region of the oxide semiconductor layer in the first addition step is lower than a concentration of the element added to the second region of the oxide semiconductor layer in the second addition step.