THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20120161131A1
• Filed: 08/24/2011
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KANG, Min, YOO, Hyeong-Suk, JU, Jin-Ho, CHANG, Chong-Sup
• Application Number:
  US13/216,326
• Publication Number:
  US 20120161131A1
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A thin-film transistor (“TFT”) substrate includes a metal wiring including copper or a copper alloy on a substrate, an inorganic layer on an upper surface and side surfaces of the metal wiring to surround the metal wiring, the inorganic layer in direct contact with the metal wiring, and a planarization layer on the inorganic layer and in direct contact with the inorganic layer.

Claims

1. A thin-film transistor substrate comprising:

a metal wiring including copper or a copper alloy on a substrate;

an inorganic layer on an upper surface and side surfaces of the metal wiring to surround the metal wiring, and in direct contact with the metal wiring; and

a planarization layer on the inorganic layer and in direct contact with the inorganic layer.

2. The thin-film transistor substrate of claim 1, wherein the metal wiring is a gate electrode, a source electrode, or a drain electrode.

3. The thin-film transistor substrate of claim 1, wherein the planarization layer includes an organic material.

4. The thin-film transistor substrate of claim 1, wherein the inorganic layer includes silicon nitride (SiNx).

5. The thin-film transistor substrate of claim 1, wherein a maximum distance between a surface of the substrate and a top surface of the planarization layer, is equal to or smaller than a maximum distance between the surface of the substrate and a top surface of the inorganic layer.

6. The thin-film transistor substrate of claim 1, wherein

the metal wiring is a gate electrode, and

the gate electrode has a thickness of about 5,000 angstroms (Å

) or more.

7. The thin-film transistor substrate of claim 1, wherein

the metal wiring is a gate electrode, and

the inorganic layer surrounds the gate electrode, and contacts a portion of the substrate excluding the gate electrode.

8. The thin-film transistor substrate of claim 1,

wherein the metal wiring is a gate electrode, and

further comprising:

an active layer on the inorganic layer, the active layer overlapping the gate electrode;

ohmic contact layers on the active layer and separated from each other with respect to the active layer; and

a source electrode and a drain electrode including copper or a copper alloy, on the ohmic contact layers.

9. The thin-film transistor substrate of claim 8, wherein the drain electrode and the source electrode have a thickness of about 5,000 angstroms (Å

) or more.

10. The thin-film transistor substrate of claim 9, further comprising a passivation layer including an inorganic material on the source electrode and the drain electrode, wherein the passivation layer is in contact with the source electrode and in contact with the drain electrode.

11. The thin-film transistor substrate of claim 1, further comprising an insulating layer on an entire surface of the substrate, and covering the inorganic layer and the planarization layer.

12. A method of manufacturing a thin-film transistor substrate, the method comprising:

forming a metal wiring including copper or a copper alloy on a substrate;

forming an inorganic layer in direct contact with an upper surface and side surfaces of the metal wiring, to surround the metal wiring;

forming an organic layer including an organic material, on the substrate; and

planarizing the organic layer by removing a predetermined portion of the organic layer, such that a maximum distance between a surface of the substrate and a top surface of the organic layer is smaller than or equal to a maximum distance between the surface of the substrate and a top surface of the inorganic layer.

13. The method of claim 12, wherein the metal wiring is formed to a thickness of about 5,000 angstroms (Å

) or more.

14. The method of claim 12, wherein in the planarizing the organic layer, an upper part of the organic layer is removed by a predetermined thickness using an ashing process.

15. The method of claim 12, wherein

the metal wiring is a gate electrode;

and

the organic material is coated on the substrate such that a top surface of the organic layer is higher than a top surface of the gate electrode.

16. The method of claim 12, wherein the organic layer is formed including the organic material, by a coating process.

17. The method of claim 12, wherein the metal wiring is a gate electrode, a source electrode, or a drain electrode.

18. A thin-film transistor substrate comprising:

a first metal wiring including copper or a copper alloy on a substrate, wherein the first metal wiring has an upper surface at a maximum thickness of the first metal wiring;

a first inorganic layer contacting the upper surface and contacting side surfaces of the first metal wiring; and

a first organic layer contacting the first inorganic layer, wherein an upper surface of the first organic layer is closer to the substrate than an upper surface of the first inorganic layer overlapping the upper surface of the first wiring.

19. The thin-film transistor substrate of claim 18,

further comprising:

a second metal wiring including copper or a copper alloy on the substrate, wherein the second metal wiring has an upper surface at a maximum thickness of the second metal wiring;

a second inorganic layer contacting the upper surface and contacting side surfaces of the second metal wiring; and

a second organic layer contacting the second inorganic layer, wherein an upper surface of the second organic layer is closer to the substrate than an upper surface of the second inorganic layer overlapping the upper surface of the second wiring; and

further comprising an insulting layer between and contacting both the second metal wiring and the first organic layer.

20. The thin-film transistor substrate of claim 19, wherein

the first metal wiring is a gate electrode, and

the second metal wiring is a source electrode and a drain electrode.