SEMICONDUCTOR DEVICE

• US 20120161220A1
• Filed: 12/23/2011
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 9,048,142 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: C04B 2235/3284 Zinc oxides, zincates, cadmium oxides, cadmiates, mercury oxides, mercurates or oxide forming salts thereof
• CPC Class Codes: C04B 2235/3286 Gallium oxides, gallates, indium oxides, indates, thallium oxides, thallates or oxide forming salts thereof, e.g. zinc gallate
• CPC Class Codes: C04B 35/58 based on borides, nitrides, i.e. nitrides, oxynitrides, carbonitrides or oxycarbonitrides or silicides containing free binder metal C22C29/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.

Claims

1. A semiconductor device comprising:

a first transistor; and

a second transistor over the first transistor,

wherein the second transistor comprises a semiconductor layer including an oxide semiconductor material,

wherein the first transistor comprises a channel formation region and an impurity region provided in a semiconductor substrate including a semiconductor material other than an oxide semiconductor, and a gate electrode including an upper surface in contact with the semiconductor layer.

2. The semiconductor device according to claim 1,

wherein the gate electrode serves as one of a source electrode and a drain electrode of the second transistor.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor material comprises a crystal which is c-axis aligned, has a triangular or hexagonal atomic arrangement when seen from the direction perpendicular to an a-b plane, and has a variation in the direction of an a-axis or a b-axis in the a-b plane.

4. A semiconductor device comprising:

a first transistor comprising;

a first impurity region, a second impurity region, and a first channel formation region provided between the first impurity region and the second impurity region, wherein the first channel formation region, the first impurity region, and the second impurity region are provided in a semiconductor substrate;

a first gate insulating layer over the first channel formation region; and

a first gate electrode over the first gate insulating layer;

an insulating layer over the first transistor; and

a second transistor over the insulating layer comprising;

a semiconductor layer including a first low-resistance region, a second low-resistance region, and a second channel formation region provided between the first low-resistance region and the second low-resistance region;

a second gate insulating layer over the semiconductor layer; and

a second gate electrode over the second gate insulating layer,

wherein the upper surface of the first gate electrode is in contact with one of the first low-resistance region and the second low-resistance region.

5. The semiconductor device according to claim 4,

wherein the first gate electrode serves as one of a source electrode and a drain electrode of the second transistor.

6. The semiconductor device according to claim 5, further comprising a conductive layer in contact with the other of the first low-resistance region and the second low-resistance region.

7. A semiconductor device according to claim 4, further comprising a conductive layer over the first gate electrode with the semiconductor layer and the second gate insulating layer sandwiched therebetween.

8. A semiconductor device according to claim 7,

wherein the stack of the first gate electrode, the semiconductor layer, the second gate insulating layer, and the conductive layer serves as a capacitor.

9. A semiconductor device according to claim 4, further comprising:

a first conductive layer over the first gate electrode with the semiconductor layer and the second gate insulating layer sandwiched therebetween, and

a second conductive layer in contact with the other of the first low-resistance region and the second low-resistance region.

10. A semiconductor device according to claim 7,

wherein the stack of the first gate electrode, the semiconductor layer, the second gate insulating layer, and the first conductive layer serves as a capacitor.

11. The semiconductor device according to claim 4,

wherein the first transistor comprises a source electrode and a drain electrode provided in contact with the first impurity region and the second impurity region, respectively.

12. The semiconductor device according to claim 4,

wherein the second gate electrode includes an In—

Ga—

Zn—

O—

N-based compound conductor.

13. The semiconductor device according to claim 4,

wherein the semiconductor layer includes an oxide semiconductor material, and

wherein the semiconductor substrate includes a semiconductor material other than an oxide semiconductor.

14. The semiconductor device according to claim 13,

wherein the oxide semiconductor material comprises a crystal which is c-axis aligned, has a triangular or hexagonal atomic arrangement when seen from the direction perpendicular to an a-b plane, and has a variation in the direction of an a-axis or a b-axis in the a-b plane.