SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

• US 20120161239A1
• Filed: 12/22/2011
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,674,351 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A data retention period of a memory circuit is lengthened, power consumption is reduced, and a circuit area is reduced. Further, the number of times written data can be read to one data writing operation is increased. A memory circuit has a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of a source and a drain of the third field-effect transistor is electrically connected to a source or a drain of the second field-effect transistor.

Claims

1. A semiconductor device comprising a memory circuit,

wherein the memory circuit comprises:

a first field-effect transistor, one of a source and a drain of which is configured to receive a data signal;

a second field-effect transistor, a gate of which is electrically connected to the other of the source and the drain of the first field-effect transistor; and

a third field-effect transistor, one of a source and a drain of which is electrically connected to a source or a drain of the second field-effect transistor,

wherein the first field-effect transistor comprises an oxide semiconductor layer including a pair of regions with a channel formed therebetween,

wherein a dopant is added to the pair of regions.

2. The semiconductor device according to claim 1, wherein at least a region of the oxide semiconductor layer, in which the channel is formed is non-single-crystal and includes a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from a direction perpendicular to an a-b plane and in which metal atoms are arranged in a layered manner when seen from a direction perpendicular to a c-axis direction or the metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.

3. The semiconductor device according to claim 1, wherein the first field-effect transistor comprises:

a source electrode provided over the oxide semiconductor layer;

a drain electrode provided over the oxide semiconductor layer;

a gate insulating layer provided over the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode provided over the gate insulating layer.

4. The semiconductor device according to claim 1, wherein each of the pair of regions comprises a region of high concentration of the dopant and a region of low concentration of the dopant which is in contact with the channel.

5. The semiconductor device according to claim 1, wherein the dopant is selected from elements belonging to Group 15 or 18.

6. A semiconductor memory device comprising:

a plurality of memory cells arranged in i rows (i is a natural number of 2 or more) and j columns (j is a natural number);

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein the memory cell comprises;

a first field-effect transistor, one of a source and a drain of which is electrically connected to the first wiring, and a gate of which is electrically connected to the second wiring;

a second field-effect transistor, one of a source and a drain of which is electrically connected to the third wiring, and a gate of which is electrically connected to the other of the source and the drain of the first field-effect transistor; and

a third field-effect transistor, one of a source and a drain of which is electrically connected to the other of the source and the drain of the second field-effect transistor, the other of the source and the drain of which is electrically connected to the fourth wiring, and a gate of which is electrically connected to the fifth wiring,

wherein the first field-effect transistor comprises an oxide semiconductor layer including a pair of regions with a channel formed therebetween,

wherein a dopant is added to the pair of regions, and

wherein the second field-effect transistor and the third field-effect transistor each include a semiconductor layer in which a channel is formed and which contains silicon.

7. The semiconductor memory device according to claim 6, wherein at least a region of the oxide semiconductor layer, in which the channel is formed is non-single-crystal and includes a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from a direction perpendicular to an a-b plane and in which metal atoms are arranged in a layered manner when seen from a direction perpendicular to a c-axis direction or the metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.

8. The semiconductor memory device according to claim 6, wherein the first field-effect transistor comprises:

a source electrode provided over the oxide semiconductor layer;

a drain electrode provided over the oxide semiconductor layer;

a gate insulating layer provided over the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode provided over the gate insulating layer.

9. The semiconductor memory device according to claim 6, wherein each of the pair of regions comprises a region of high concentration of the dopant and a region of low concentration of the dopant which is in contact with the channel.

10. The semiconductor memory device according to claim 6, wherein the dopant is selected from elements belonging to Group 15 or 18.

11. A semiconductor memory device comprising:

a plurality of memory cells arranged in i rows (i is a natural number of 2 or more) and j columns (j is a natural number);

a first wiring;

a second wiring;

a third wiring; and

a fourth wiring,

wherein the memory cell comprises;

a first field-effect transistor, one of a source and a drain of which is electrically connected to the first wiring, and a gate of which is electrically connected to the second wiring;

a second field-effect transistor, one of a source and a drain of which is electrically connected to the third wiring, and a gate of which is electrically connected to the other of the source and the drain of the first field-effect transistor; and

a third field-effect transistor, one of a source and a drain of which is electrically connected to the other of the source and the drain of the second field-effect transistor, the other of the source and the drain of which is electrically connected to the first wiring, and a gate of which is electrically connected to the fourth wiring,

wherein the first field-effect transistor comprises an oxide semiconductor layer including a pair of regions with a channel formed therebetween,

wherein a dopant is added to the pair of regions, and

wherein the second field-effect transistor and the third field-effect transistor each include a semiconductor layer in which a channel is formed and which contains silicon.

12. The semiconductor memory device according to claim 11, wherein at least a region of the oxide semiconductor layer, in which the channel is formed is non-single-crystal and includes a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from a direction perpendicular to an a-b plane and in which metal atoms are arranged in a layered manner when seen from a direction perpendicular to a c-axis direction or the metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.

13. The semiconductor memory device according to claim 11, wherein the first field-effect transistor comprises:

a source electrode provided over the oxide semiconductor layer;

a drain electrode provided over the oxide semiconductor layer;

a gate insulating layer provided over the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode provided over the gate insulating layer.

14. The semiconductor memory device according to claim 11, wherein each of the pair of regions comprises a region of high concentration of the dopant and a region of low concentration of the dopant which is in contact with the channel.

15. The semiconductor memory device according to claim 11, wherein the dopant is selected from elements belonging to Group 15 or 18.