Monolithic IGBT and diode structure for quasi-resonant converters

• US 20120161286A1
• Filed: 12/23/2010
• Published: 06/28/2012
• Est. Priority Date: 12/23/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup
• Granted Patent: US 8,502,346 B2
• Time in Patent Office: Days
• US Class Current: 257/577
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/0647 Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

Claims

1. A semiconductor device comprising:

a vertical semiconductor device formed in a semiconductor substrate;

a peripheral terminal of a diode located in a termination area of the vertical semiconductor device;

a central terminal of the diode disposed in an active area of the semiconductor device laterally away from the peripheral terminal.

2. The semiconductor device of claim 1 further comprising:

a channel stop region located in a termination area of the semiconductor device near the periphery of the semiconductor substrate, wherein the peripheral terminal contacts the semiconductor substrate at the channel stop region.

3. The semiconductor device of claim 1 wherein:

a vertical insulated gate bipolar transistor (IGBT) integrated with the diode disposed laterally from the active area of the IGBT to the termination area.

4. The semiconductor device of claim 1 further comprising:

an electric field spreading termination structure disposed in the termination area between the active area of the semiconductor power device and the peripheral terminal of the diode.

5. The semiconductor device of claim 1 wherein:

the peripheral terminal of the diode further comprises a conductive plug filling in a peripheral contact trench near a periphery of the semiconductor substrate covered by a peripheral metal contact disposed on top of the conductive plug.

6. The semiconductor device of claim 1 wherein:

the central terminal of the diode further comprises a conductive plug filling in a central contact trench disposed in the active area of the semiconductor substrate covered by a central metal contact disposed on top of the conductive plug.

7. The semiconductor device of claim 1 wherein:

the semiconductor device comprises a vertical insulated gate bipolar transistor (IGBT) combined with the diode disposed laterally across from the active area of the IGBT to the peripheral terminal in the termination area wherein said vertical IGBT includes a collector terminal disposed on a bottom surface of the semiconductor substrate and an emitter terminal disposed on a top surface of the semiconductor substrate, wherein the emitter terminal is the central terminal of the diode.

8. The semiconductor device of claim 7 wherein:

said vertical IGBT is formed in a first semiconductor layer of a first conductivity type and the vertical IGBT further comprises a gate in the active area, said gate being adjacent to a body region of a second conductivity type encompassing a source region of the first conductivity type, wherein the vertical IGBT further includes a collector layer of a second conductivity type located below said first semiconductor layer.

9. The semiconductor device of claim 8 further comprising:

a buffer layer of the first conductivity type located between the collector layer and the first semiconductor layer, wherein the buffer layer is more heavily doped than the first semiconductor layer.

10. The semiconductor device of claim 7 further comprising:

a termination structure disposed in the first semiconductor layer between the active area of the vertical IGBT and the peripheral terminal of the diode.

11. The semiconductor device of claim 7 wherein:

the peripheral terminal of the diode further comprises a conductive plug filling in a peripheral trench near a periphery of the semiconductor substrate and covered by cathode metal contact disposed on top of the conductive plug wherein said peripheral trench contacts an upper dopant region of said first conductivity type and a lower heavily dopant region of said second conductivity type below the upper dopant region.

12. The semiconductor device of claim 7 wherein:

the central terminal of the diode further comprises a conductive plug filling in a central trench contacting said body and source region of the vertical IGBT and covered by an emitter/anode metal contact disposed on top of the conductive plug; and

a lightly doped region of said second conductivity type disposed in said first semiconductor layer immediately below a bottom surface of the central trench such that the diode is a low injection efficiency diode.

13. The semiconductor device of claim 7 further comprising:

a conductive via opened through the semiconductor substrate as a through-semiconductor-via (TSV) internally connecting the peripheral terminal to the collector terminal.

14. The semiconductor device of claim 7 further comprising:

a channel stop region located in a termination area of the semiconductor device near the periphery of the semiconductor substrate, wherein the peripheral terminal contacts the semiconductor substrate at the channel stop region.

15. A package assembly for a vertical semiconductor device therein wherein:

said vertical semiconductor device is formed in a semiconductor substrate having a peripheral terminal of a lateral diode in a termination area of the vertical semiconductor device and a central terminal of the diode laterally opposite from the peripheral terminal, the central terminal being disposed on an active area of the vertical semiconductor device; and

a leadframe having conductive interconnections connected to said peripheral and central terminals of said lateral diode and said vertical semiconductor device.

16. The package assembly of claim 15 wherein:

the semiconductor device comprises a vertical insulated gate bipolar transistor (IGBT) combined with the lateral diode disposed laterally from the active area of the IGBT and the termination area wherein said vertical IGBT includes a collector terminal disposed on a bottom surface of the semiconductor substrate and an emitter terminal disposed on a top surface of the semiconductor substrate; and

said leadframe include a die pad for supporting the bottom surface of the semiconductor substrate and contacting the collector terminal of said vertical IGBT.

17. The package assembly of claim 16 further comprising:

a conductive interconnection electrically connects said peripheral terminal of the diode to the collector terminal of the IGBT device through the die pad.

18. A method for forming a semiconductor device comprising:

manufacturing a vertical semiconductor device in a semiconductor substrate and integrating a lateral diode with the vertical semiconductor device;

forming a peripheral terminal of the diode in a termination area of the vertical semiconductor device; and

forming a central terminal of the lateral diode in an active area of the vertical semiconductor device laterally spaced from the central terminal.

19. The method of claim 18 wherein:

the step of manufacturing said semiconductor device is a step of manufacturing a vertical insulated gate bipolar transistor (IGBT) wherein the lateral diode is disposed laterally from the active area of the IGBT to the termination area of the IGBT with a collector terminal of said vertical IGBT formed on a bottom surface of the semiconductor substrate and an emitter terminal formed on a top surface of the semiconductor substrate.

20. The method of claim 19 further comprising:

mounting said vertical IGBT onto a die pad of a leadframe, said die pad electrically contacting the collector terminal of said vertical IGBT.

21. The method of claim 20 further comprising:

connecting a conductive interconnection from the peripheral terminal of the lateral diode to leadframe, thereby electrically connecting the peripheral terminal of the lateral diode to the collector terminal of the IGBT through the die pad.