CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE

• US 20120161827A1
• Filed: 12/27/2011
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Abandoned Application

• Current Assignee: Stmicroelectronics Canada Incorporated (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Canada Incorporated (STMicroelectronics NV)
• Inventors: Hogeboom, John, Madeira, Paul, Hogeboom-Nivera, Pat
• Application Number:
  US13/338,111
• Publication Number:
  US 20120161827A1
• Time in Patent Office: Days
• US Class Current: 327/147
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.

Claims

1. A clock circuit comprising:

a comparator for receiving a reference clock signal;

a first VCO coupled to the comparator;

a feedback divider coupled between the first VCO and the comparator;

a clock distribution chain coupled to the feedback divider and the first VCO; and

a second VCO coupled to the clock distribution chain for providing an output clock signal.

2. The clock circuit of claim 1 wherein the comparator comprises a frequency comparator.

3. The clock circuit of claim 1 wherein the comparator comprises a phase comparator.

4. The clock circuit of claim 1 wherein the reference clock signal comprises a 125 MHz reference clock signal.

5. The clock circuit of claim 1 wherein the first VCO comprises an LC VCO.

6. The clock circuit of claim 1 wherein the first VCO comprises a 6.25 GHz VCO.

7. The clock circuit of claim 1 wherein the feedback divider comprises a divide by 50 feedback divider.

8. The clock circuit of claim 1 wherein the clock distribution chain comprises a single phase clock distribution chain including a plurality of buffer circuits.

9. The clock circuit of claim 1 further comprising the second VCO comprises a plurality of VCOs for providing a plurality of multiple phase output clock signals.

10. The clock circuit of claim 1 wherein the second VCO comprises a DLL or an injection-locked ring-VCO.

11. A clock circuit comprising:

a comparator for receiving a reference clock signal;

a first VCO coupled to the comparator, wherein the first VCO is a first type of VCO circuit;

a feedback divider coupled between the first VCO and the comparator;

a clock distribution chain coupled to the feedback divider and the first VCO; and

a second VCO coupled to the clock distribution chain for providing an output clock signal, wherein the second VCO is a second type of VCO circuit.

12. The clock circuit of claim 11 wherein the comparator comprises a frequency comparator.

13. The clock circuit of claim 11 wherein the comparator comprises a phase comparator.

14. The clock circuit of claim 11 wherein the reference clock signal comprises a 125 MHz reference clock signal.

15. The clock circuit of claim 11 wherein the first VCO comprises an LC VCO.

16. The clock circuit of claim 11 wherein the first VCO comprises a 6.25 GHz VCO.

17. The clock circuit of claim 11 wherein the feedback divider comprises a divide by 50 feedback divider.

18. The clock circuit of claim 11 wherein the clock distribution chain comprises a single phase clock distribution chain including a plurality of buffer circuits.

19. The clock circuit of claim 11 further comprising the second VCO comprises a plurality of VCOs for providing a plurality of multiple phase output clock signals.

20. The clock circuit of claim 11 wherein the second VCO comprises a DLL or an injection-locked ring-VCO.

21. A method of providing a plurality of phased clock signals comprising:

comparing a reference clock signal to a feedback signal;

transferring a result of the comparison to a first VCO;

dividing an output signal provided by the first VCO to generate the feedback signal; and

providing the output signal to a plurality of second VCOs to generate the plurality of phased clock signals, wherein the first VCO and second VCO are different types of VCO circuits.