CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE
First Claim
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1. A clock circuit comprising:
- a comparator for receiving a reference clock signal;
a first VCO coupled to the comparator;
a feedback divider coupled between the first VCO and the comparator;
a clock distribution chain coupled to the feedback divider and the first VCO; and
a second VCO coupled to the clock distribution chain for providing an output clock signal.
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Abstract
A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.
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Citations
21 Claims
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1. A clock circuit comprising:
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a comparator for receiving a reference clock signal; a first VCO coupled to the comparator; a feedback divider coupled between the first VCO and the comparator; a clock distribution chain coupled to the feedback divider and the first VCO; and a second VCO coupled to the clock distribution chain for providing an output clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A clock circuit comprising:
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a comparator for receiving a reference clock signal; a first VCO coupled to the comparator, wherein the first VCO is a first type of VCO circuit; a feedback divider coupled between the first VCO and the comparator; a clock distribution chain coupled to the feedback divider and the first VCO; and a second VCO coupled to the clock distribution chain for providing an output clock signal, wherein the second VCO is a second type of VCO circuit. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of providing a plurality of phased clock signals comprising:
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comparing a reference clock signal to a feedback signal; transferring a result of the comparison to a first VCO; dividing an output signal provided by the first VCO to generate the feedback signal; and providing the output signal to a plurality of second VCOs to generate the plurality of phased clock signals, wherein the first VCO and second VCO are different types of VCO circuits.
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Specification