Flat panel display apparatus

• US 20120162050A1
• Filed: 08/19/2011
• Published: 06/28/2012
• Est. Priority Date: 12/23/2010
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Zhan, Zhi-Feng, Tae, Seung-Gyu, Moon, Sung-Hoon, Kim, Deok-Hoi
• Granted Patent: US 8,723,770 B2
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: G06F 1/00 Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 architectures of general purpose stored program computers G06F15/76
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A flat panel display apparatus includes a first pixel region on a substrate and defined by an intersection between a first gate line and a data line. The first pixel region includes a first transistor and a first capacitor and is covered by a first pixel electrode. The apparatus includes a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line. The second pixel region is covered by a second pixel electrode. The first gate line is positioned between the first pixel electrode and the second pixel electrode. A second capacitor is in the second pixel region, and the second capacitor includes a first transparent conductive layer and a second transparent conductive layer. A transparent shielding portion extends from the second transparent conductive layer of the second capacitor toward the first pixel region to overlap with the first gate line.

Claims

1. A flat panel display apparatus, comprising:

a first pixel region on a substrate and defined by an intersection between a first gate line and a data line, the first pixel region including a first transistor and a first capacitor, and the first pixel region being covered by a first pixel electrode;

a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line, the second pixel region being covered by a second pixel electrode;

the first gate line positioned between the first pixel electrode and the second pixel electrode;

a second capacitor included in the second pixel region, the second capacitor including a first transparent conductive layer and a second transparent conductive layer; and

a transparent shielding portion extending from the second transparent conductive layer of the second capacitor toward the first pixel region to overlap with the first gate line.

2. The flat panel display apparatus as claimed in claim 1, wherein the transparent shielding portion includes:

a shielding portion extending in a same direction as an extending direction of the first gate line to overlap the first gate line; and

a connecting portion extending toward the first pixel region to connect the shielding portion with the second transparent conductive layer.

3. The flat panel display apparatus as claimed in claim 1, wherein the first transparent conductive layer, the second transparent conductive layer, and the transparent shielding portion include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

4. The flat panel display apparatus as claimed in claim 1, further comprising a second transistor in the second pixel region and connected to the second pixel electrode, wherein the second transistor includes:

a semiconductor layer on the substrate, the semiconductor layer including a channel region, a source region, and a drain region;

a gate electrode on the channel region with a first insulating layer between the gate electrode and the channel region, the gate electrode protruding from the second gate line; and

a source electrode and a drain electrode of the second transistor connected to the source region and the drain region through a second insulating layer and a third insulating layer on the gate electrode.

5. The flat panel display apparatus as claimed in claim 4, further comprising an organic layer between the second pixel electrode and the source and drain electrodes, one of the source electrode and the drain electrode being connected to the second pixel electrode through a via-hole in the organic layer.

6. The flat panel display apparatus as claimed in claim 4, wherein the second capacitor includes a capacitor wiring line formed of a same material and in a same layer as the gate electrode, the capacitor wiring line directly contacting the first transparent conductive layer.

7. The flat panel display apparatus as claimed in claim 6, wherein:

the first transparent conductive layer is on the capacitor wiring line; and

the second transparent conductive layer corresponds to the first transparent conductive layer, the second insulating layer being between the second transparent conductive layer and the first transparent conductive layer, and

the second transparent conductive layer is connected to one of the source electrode and the drain electrode of the second transistor.

8. The flat panel display apparatus as claimed in claim 6, wherein the capacitor wiring line includes a conductive material, the conductive material including at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW, Al/Cu, and Cu.

9. The flat panel display apparatus as claimed in claim 1, wherein the first transistor is connected to the first pixel electrode and includes a gate electrode protruding from the first gate line.

10. The flat panel display apparatus as claimed in claim 1, further comprising an opposing electrode facing the first pixel electrode and the second pixel electrode, wherein liquid crystal is between the first and second pixel electrodes and the opposing electrode.

11. The flat panel display apparatus as claimed in claim 10, wherein:

the second capacitor includes a capacitor wiring line formed of a same material and in a same layer as the second gate line, the capacitor wiring line directly contacting the first transparent conductive layer, and

a common voltage is supplied to the capacitor wiring line.

12. A flat panel display apparatus, comprising:

a first pixel region on a substrate and defined by an intersection between a first gate line and a data line, the first pixel region being covered by a first pixel electrode;

a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line, the second pixel region being covered by a second pixel electrode;

the first gate line positioned between the first pixel electrode and the second pixel electrode;

a first capacitor included in the first pixel region, the first capacitor including a first transparent conductive layer and a second transparent conductive layer; and

a transparent shielding portion extending from the second transparent conductive layer of the first capacitor toward the second pixel region to overlap with the first gate line.

13. The flat panel display apparatus as claimed in claim 12, wherein the transparent shielding portion includes:

a shielding portion extending in a same direction as an extending direction of the first gate line to overlap the first gate line; and

a connecting portion extending toward the second pixel region to connect the shielding portion with the second transparent conductive layer.

14. The flat panel display apparatus as claimed in claim 12, wherein the first transparent conductive layer, the second transparent conductive layer, and the transparent shielding portion include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

15. The flat panel display apparatus as claimed in claim 12, further comprising a first transistor in the first pixel region and connected to the first pixel electrode, wherein the first transistor includes:

a semiconductor layer on the substrate, the semiconductor layer including a channel region, a source region, and a drain region;

a gate electrode on the channel region with a first insulating layer between the gate electrode and the channel region, the gate electrode protruding from the first gate line; and

a source electrode and a drain electrode of the first transistor connected to the source region and the drain region through a second insulating layer and a third insulating layer on the gate electrode.

16. The flat panel display apparatus as claimed in claim 15, further comprising an organic layer between the first pixel electrode and the source and drain electrodes, one of the source electrode and the drain electrode being connected to the first pixel electrode through a via-hole in the organic layer.

17. The flat panel display apparatus as claimed in claim 15, wherein the first capacitor includes a capacitor wiring line formed of a same material and in a same layer as the gate electrode, the capacitor wiring line directly contacting the first transparent conductive layer.

18. The flat panel display apparatus as claimed in claim 17, wherein:

the first transparent conductive layer is on the capacitor wiring line; and

the second transparent conductive layer corresponds to the first transparent conductive layer, the second insulating layer being between the second transparent conductive layer and the first transparent conductive layer; and

the second transparent conductive layer is connected to one of the source electrode and the drain electrode of the first transistor.

19. The flat panel display apparatus as claimed in claim 17, wherein the capacitor wiring line includes a conductive material, the conductive material including at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW, Al/Cu, and Cu.

20. The flat panel display apparatus as claimed in claim 12, further comprising an opposing electrode facing the first pixel electrode, wherein liquid crystal is between the first pixel electrode and the opposing electrode.

21. The flat panel display apparatus as claimed in claim 20, wherein:

the first capacitor includes a capacitor wiring line formed of a same material in a same layer as the first gate line, the capacitor wiring line directly contacting the first transparent conductive layer; and

a common voltage is supplied to the capacitor wiring line.