TOUCH SCREEN TRANSISTOR DOPING PROFILES

• US 20120162089A1
• Filed: 12/22/2010
• Published: 06/28/2012
• Est. Priority Date: 12/22/2010
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: CHANG, Shih Chang
• Application Number:
  US12/976,778
• Publication Number:
  US 20120162089A1
• Time in Patent Office: Days
• US Class Current: 345/173
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G09G 2310/0264 Details of driving circuits
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Variations in capacitances of semiconductor circuit elements, such as pixel TFTs, of touch screens can be reduced or eliminated by selectively doping different regions of the semiconductor circuit element. For example, the semiconductor circuit element can include a semiconductive channel of a transistor, such as a pixel TFT. A dopant concentration profile of the semiconductive channel can be selected to reduce or eliminate variations in a gate-to-drain capacitance caused by voltage variations at the drain.

Claims

1. A touch screen comprising:

a drive line that carries a stimulation signal during a touch sensing phase;

a sense line that receives a sense signal during the touch sensing phase, the sense signal being based on the stimulation signal;

a display circuit element that maintains a voltage during the touch sensing phase;

a voltage supply system that supplies the voltage to the display circuit element during a display phase;

a transistor with a drain connected to the display circuit element and a source connected to the voltage supply system, the transistor including one or more gates, at least one gate being a gate closest to the drain, and a semiconductive channel including a first region of a first concentration of dopant, the first region disposed between the drain and the gate closest to the drain, and a second region of a second concentration of dopant, the second region disposed between the source and the gate closest to the drain, wherein the first concentration of dopant is greater than the second concentration of dopant; and

a control system that, during the display phase, switches the transistor to an on state, controls the voltage supply system to supply the voltage to the display circuit element during the on state of the transistor, and switches the transistor to an off state after the display circuit element is supplied with the voltage and prior to the touch sensing phase, such that the transistor is held in the off state during touch sensing.

2. The touch screen of claim 1, wherein the display circuit element includes a pixel electrode.

3. The touch screen of claim 1, wherein the transistor includes a thin film transistor.

4. The touch screen of claim 1, wherein the first region extends from the drain to the gate closest to the drain.

5. The touch screen of claim 1, wherein the semiconductive channel further includes a third region of the first concentration of dopant, the third region disposed between the source and the gate closest to the drain.

6. The touch screen of claim 5, wherein the third region is disposed between the second region and the source.

7. The touch screen of claim 6, wherein a dopant concentration profile of the semiconductive channel includes the first, second, and third regions, and the dopant concentration profile is symmetrical about a midpoint along the length of the semiconductive channel.

8. The touch screen of claim 1, wherein a dopant concentration profile of the semiconductive channel includes the first and second regions, and the dopant concentration profile is asymmetrical about a midpoint along the length of the semiconductive channel.

9. A touch screen system comprising:

an integrated touch sensing system including a drive portion that generates stimulation signals and applies the stimulation signals to a plurality of first circuit elements within display pixel stackups of a touch screen panel, and a sense portion including second circuit elements within the display pixel stackups, the second circuit elements receiving first signals based on the stimulation signals, the first signal being sense signals;

a plurality of third circuit elements within the display pixel stackups, the third circuit elements receiving second signals based on the stimulation signals;

a plurality of transistors, each transistor including one or more gates, a drain connected to one of the third circuit elements, and a semiconductive channel including a first region of a first concentration of dopant, the first region disposed between the drain and a gate closest to the drain, and a second region of a second concentration of dopant, the second region disposed between a source of the transistor and the gate closest to the drain, wherein the first concentration of dopant is greater than the second concentration of dopant; and

an electrical pathway connecting one of the third circuit elements to one of the second circuit elements, the electrical pathway including a gate-to-drain capacitance of the transistor connected to the third circuit element, wherein the second signal is coupled to the second circuit element through the electrical pathway.

10. The touch screen system of claim 9, wherein the electrical pathway further includes a gate-to-drain capacitance of another of the plurality of transistors.

11. The touch screen system of claim 9, wherein the third circuit elements include pixel electrodes.

12. The touch screen system of claim 9, wherein the electrical pathway further includes a gate line of the touch screen.

13. The touch screen system of claim 9, wherein the first region extends from the drain to the gate closest to the drain.

14. The touch screen system of claim 9, wherein the semiconductive channel further includes a third region of the first concentration of dopant, the third region disposed between the source and the gate closest to the drain.

15. The touch screen system of claim 14, wherein the third region is disposed between the second region and the source.

16. The touch screen system of claim 14, wherein a dopant concentration profile of the semiconductive channel includes the first, second, and third regions, and the dopant concentration profile is symmetrical about a midpoint along the length of the semiconductive channel.

17. The touch screen system of claim 9, wherein a dopant concentration profile of the semiconductive channel includes the first and second regions, and the dopant concentration profile is asymmetrical about a midpoint along the length of the semiconductive channel.

18. The touch screen system of claim 9, further comprising a voltage supply system that supplies a voltage to the plurality of third circuit elements during a display phase of the touch screen.

19. The touch screen system of claim 18, wherein the voltage supply system is connected to the sources of the transistors, and the voltage is supplied to the third circuit elements during an on state of the corresponding transistors.

20. A computer system comprising:

a processor;

a memory; and

an integrated touch screen including

a drive line that carries a stimulation signal during a touch sensing phase,

a sense line that receives a sense signal during the touch sensing phase, the sense signal being based on the stimulation signal,

a display circuit element that maintains a voltage during the touch sensing phase,

a voltage supply system that supplies the voltage to the display circuit element during a display phase,

a transistor with a drain connected to the display circuit element and a source connected to the voltage supply system, the transistor including one or more gates, at least one gate being a gate closest to the drain, and a semiconductive channel including a first region of a first concentration of dopant, the first region disposed between the drain and the gate closest to the drain, and a second region of a second concentration of dopant, the second region disposed between the source and the gate closest to the drain, wherein the first concentration of dopant is greater than the second concentration of dopant, and

a control system that, during the display phase, switches the transistor to an on state, controls the voltage supply system to supply the voltage to the display circuit element during the on state of the transistor, and switches the transistor to an off state after the display circuit element is supplied with the voltage and prior to the touch sensing phase, such that the transistor is held in the off state during touch sensing.

21. A method of manufacturing an integrated touch screen, the method comprising:

forming plurality of display pixel stackups including

a plurality of drive lines,

a plurality of sense lines,

a plurality of gate lines,

a plurality of data lines,

a plurality of pixel electrodes, and

a plurality of transistors, each transistor including a drain connected to one of the pixel electrodes and a source connected to one of the data lines, the transistor including one or more gates connected to one of the gate lines, at least one gate being a gate closest to the drain, and a semiconductive channel including a first region of a first concentration of dopant, the first region disposed between the drain and the gate closest to the drain, and a second region of a second concentration of dopant, the second region disposed between the source and the gate closest to the drain, wherein the first concentration of dopant is greater than the second concentration of dopant.

22. The method of claim 21, wherein the first region extends from the drain to the gate closest to the drain.

23. The method of claim 21, wherein the semiconductive channel further includes a third region of the first concentration of dopant, the third region disposed between the source and the gate closest to the drain.

24. The method of claim 23, wherein the third region is disposed between the second region and the source.

25. The method of claim 24, wherein a dopant concentration profile of the semiconductive channel includes the first, second, and third regions, and the dopant concentration profile is symmetrical about a midpoint along the length of the semiconductive channel.

26. The method of claim 21, wherein a dopant concentration profile of the semiconductive channel includes the first and second regions, and the dopant concentration profile is asymmetrical about a midpoint along the length of the semiconductive channel.