CONCURRENT OPERATION OF PLURAL FLASH MEMORIES
First Claim
1. A device comprising:
- an address storage device;
a first circuit including a first flash memory, the first circuit configured to sequentially receive first and second addresses and store the first address in the address storage device, the first circuit having a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses;
a second circuit including a second flash memory, the second circuit configured to receive the second address, the second circuit having a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
1 Assignment
0 Petitions
Accused Products
Abstract
A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
9 Citations
20 Claims
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1. A device comprising:
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an address storage device; a first circuit including a first flash memory, the first circuit configured to sequentially receive first and second addresses and store the first address in the address storage device, the first circuit having a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses; a second circuit including a second flash memory, the second circuit configured to receive the second address, the second circuit having a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A device comprising:
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a first circuit including a first flash memory and a charge pump that provides a high voltage signal to the first flash memory, the first circuit having a first set of control inputs for causing the first circuit to perform an erase, program or read operation to the first flash memory; and a second circuit including a second flash memory, the second flash memory being configured without a charge pump, the second flash memory connected to use the high voltage signal from the charge pump of the first circuit, the second circuit having a second set of control inputs independent from the first set of control inputs for causing the second circuit to read from the second flash memory while the erase, program or read operation is being performed. - View Dependent Claims (13, 14, 15, 16)
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17. A method comprising:
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receiving a first address and a second address using an address input of an integrated circuit (IC) package having a first circuit contained therein, the first circuit having a first flash memory; selecting one of the group consisting of the first address and the second address; performing a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to the selected address; providing the second address to a second circuit in the IC package having a second flash memory; and reading a cell of the second flash memory corresponding to the second address while the first operation is being performed. - View Dependent Claims (18, 19, 20)
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Specification